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1. 发明专利

JP2008258199A Heat transfer sheet, and heat dissipation structure 有权
标题翻译：热转印片和散热结构
公开(公告)号：JP2008258199A
公开(公告)日：2008-10-23
申请号：JP2007095528
申请日：2007-03-30
申请人： Sumitomo Bakelite Co Ltd , Toyota Motor Corp , Toyota Tsusho Corp , トヨタ自動車株式会社 , 住友ベークライト株式会社 , 豊田通商株式会社
发明人： MURATA TAKASHI , NAKAMURA KOJI , TAKAHASHI IZUMI , SO HATSUHIRO , SHIMIZU KAZUMOTO , ARAI YOSHIHIDE , ITO SHINICHIRO , KAWAGUCHI HITOSHI , SUGINO MITSUO
IPC分类号： H01L23/36 , H05K7/20
CPC分类号： F28F3/02 , B23P15/26 , C09K5/14 , F28F2013/006 , H01L23/34 , H01L23/3733 , H01L23/3737 , H01L23/433 , H01L2924/0002 , Y10T29/49352 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a heat transfer sheet which can keep the temperature of a heat dissipation object within a desired range by preventing both supercooling and excessive temperature rise under an environment of wide temperature range from low temperature to high temperature, and to provide a heat dissipation structure employing that heat transfer sheet.
SOLUTION: The heat transfer sheet 1 comprises a heat transfer layer 3 having a first part 31 and a second part 32 provided at a position different from the first part 31 in the plan view and expanding/contracting at a bigger expansion/contraction rate than the first part 31 in the thickness direction depending on the temperature variation. The transfer sheet 1 is arranged to make an air gap 33 between the second part 32 and a partner body 5 when the temperature of the heat transfer layer 3 is below a predetermined level under use state, thus reducing thermal conductivity between a heat dissipation object 4 and the partner body 5, and to eliminate the air gap 33 substantially when the temperature of the heat transfer layer 3 is above a predetermined level, thus enhancing thermal conductivity between a heat dissipation object 4 and the partner body 5.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种传热片，其能够在从低温到高温的宽温度范围的环境中防止过冷和过度的温度升高，从而将散热物体的温度保持在期望的范围内，并提供采用该传热片的散热结构。解决方案：传热片1包括传热层3，其具有在平面图中设置在与第一部分31不同的位置处的第一部分31和第二部分32，并且以更大的伸缩收缩速率比第一部分31在厚度方向上取决于温度变化。当转印层1在使用状态下传热层3的温度低于预定水平时，转印纸1被布置成在第二部分32和对方体5之间形成气隙33，从而降低散热物体4 和配对体5，并且当传热层3的温度高于预定水平时，基本上消除气隙33，从而提高散热物体4和配对体5之间的导热性。版权所有：（C）2009，JPO＆INPIT

2. 发明专利

JP2007194353A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007194353A
公开(公告)日：2007-08-02
申请号：JP2006010076
申请日：2006-01-18
申请人： Sumitomo Bakelite Co Ltd , 住友ベークライト株式会社
发明人： KAWAGUCHI HITOSHI , HIROSE HIROSHI , TANAKA HIROYUKI
IPC分类号： H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of which cutting of a conductor layer is surely prevented. SOLUTION: A semiconductor device 1 comprises a substrate 3, a semiconductor element 4 mounted on the substrate 3, and a joint 5 containing a metal for connecting the substrate 3 to the semiconductor element 4. The substrate 3 has an insulating layer 311 containing resin and a conductor wiring layer 312 laminated alternately. The conductor wiring layers 312 are connected by a conductor layer 313 formed in a via hole 311A of the insulating layer 311. α 2Z (Tm-Tg) equals to 0.1×10 -2 to 1.8×10 -2 , where the linear expansion factor in thickness direction of the substrate 3 at a temperature T2 higher than the glass transition point (Tg) of the substrate 3 is α 2Z , melting point of the joint part 5 is Tm, and the glass transition point of the substrate 3 is Tg. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供可靠地防止导体层的切割的半导体器件。解决方案：半导体器件1包括基板3，安装在基板3上的半导体元件4和包含用于将基板3连接到半导体元件4的金属的接头5。基板3具有绝缘层311 交替地层叠的导体配线层312。导体布线层312通过形成在绝缘层311的通路孔311A中的导体层313连接.Mn 2 SB（Tm-Tg）等于0.1×10 -2 < 在高于基板3的玻璃化转变温度（Tg）的温度T2下，基板3的厚度方向的线膨胀系数为＆lt; SB＆gt;〜＆lt; SP＆gt; 2Z ，接合部5的熔点为Tm，基板3的玻璃化转变点为Tg。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006286853A Silicon interposer and semiconductor device 审中-公开
标题翻译：硅插件和半导体器件
公开(公告)号：JP2006286853A
公开(公告)日：2006-10-19
申请号：JP2005103574
申请日：2005-03-31
申请人： Sumitomo Bakelite Co Ltd , 住友ベークライト株式会社
发明人： KAWAGUCHI HITOSHI
IPC分类号： H01L23/52 , H01L23/14 , H01L23/32 , H01L25/04 , H01L25/18
CPC分类号： H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor package having excellent high-speed signal-transmission characteristics in a semiconductor package with a plurality of loaded semiconductor elements.
SOLUTION: An interposer uses a silicon single-crystal wafer 101 as a component. In the interposer, a first insulating resin layer 102 having a dielectric constant from 2.4 to 3.2 and a silicon interposer 107 with conductor circuits 105 for connecting the semiconductor elements loaded on the interposer and external connecting terminals are formed on the wafer. The insulating resin layer has low residual strain. In a semiconductor device, the semiconductor elements are loaded on the silicon interposer 107, the conductor circuits 105 on the silicon interposer 107 and the semiconductor elements are connected electrically, and the semiconductor elements and the external connecting terminals are connected through the conductor circuits 105.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在具有多个负载的半导体元件的半导体封装中具有优异的高速信号传输特性的半导体封装的制造方法。解决方案：插入器使用硅单晶晶片101作为组件。在该插入件中，在晶片上形成介电常数为2.4〜3.2的第一绝缘树脂层102和用于连接加载在插入件上的半导体元件的导体电路105和外部连接端子的硅插入件107。绝缘树脂层具有较低的残余应变。在半导体器件中，半导体元件被加载到硅插入器107上，硅插入器107上的导体电路105和半导体元件被电连接，并且半导体元件和外部连接端子通过导体电路105连接。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2005123567A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005123567A
公开(公告)日：2005-05-12
申请号：JP2004127261
申请日：2004-04-22
申请人： Disco Abrasive Syst Ltd , Ibiden Co Ltd , J−SiP Walton株式会社 , J-Sip Walton Kk , Sumitomo Bakelite Co Ltd , Toppan Printing Co Ltd , イビデン株式会社 , 住友ベークライト株式会社 , 凸版印刷株式会社 , 株式会社ディスコ
发明人： KAWAGUCHI HITOSHI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L24/73 , H01L2224/16225 , H01L2224/16245 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/73265 , H01L2924/19107 , H01L2924/00012 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a technology of manufacturing efficiently a package which contains a plurality of semiconductor chips.
SOLUTION: A method of manufacturing the semiconductor device first seals the semiconductor chip with resin to form a seal (S10), and performs polishing/thin filming for the seal (S12). Continuously, the operation of the seal (S14) is inspected, and a laminate is formed by laminating with other semiconductor chip or the seal using only a good article (S18). Then, the laminate is sealed with the resin (S20). Thus, the semiconductor device is obtained.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种高效制造包含多个半导体芯片的封装的技术。解决方案：制造半导体器件的方法首先用树脂密封半导体芯片以形成密封（S10），并对密封进行抛光/薄膜化（S12）。连续地检查密封件的操作（S14），并且通过仅使用良好的制品与其它半导体芯片或密封件层压而形成层压体（S18）。然后，用树脂密封层压体（S20）。因此，获得了半导体器件。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2004221555A Semiconductor element with film pasted, semiconductor device, and manufacturing method therefor 审中-公开
公开(公告)号：JP2004221555A
公开(公告)日：2004-08-05
申请号：JP2003421636
申请日：2003-12-18
申请人： Disco Abrasive Syst Ltd , Hitachi Chem Co Ltd , Ibiden Co Ltd , J−SiP Walton株式会社 , J-Sip Walton Kk , Sumitomo Bakelite Co Ltd , Toppan Printing Co Ltd , イビデン株式会社 , 住友ベークライト株式会社 , 凸版印刷株式会社 , 日立化成工業株式会社 , 株式会社ディスコ
发明人： KAWAGUCHI HITOSHI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L24/27 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a technique to miniaturize a semiconductor device including semiconductor elements as well as a technique to easily manufacture such a semiconductor device.
SOLUTION: The semiconductor elements 106 with a film pasted are manufactured by going through the steps of pasting a film 104 all over the surface opposite to the device formation surface of a semiconductor substrate 101 where a plurality of devices are formed, selectively removing the film 104 along the outer edge of each device with a specified width, slicing the semiconductor substrate 101 along the outer edge simultaneously with or after the step of selectively removing the film 104, and dividing it into a plurality of semiconductor elements 102 to which the film 104 is pasted that is formed to be smaller than the formation area. A plurality of semiconductor elements 106 formed with a film pasted are laminated to manufacture semiconductor devices. In this way, a semiconductor device including semiconductor elements can be miniaturized. Further, according to this invention, it is possible to manufacture such a semiconductor device with ease.
COPYRIGHT: (C)2004,JPO&NCIPI

6. 发明专利

JP2004047725A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004047725A
公开(公告)日：2004-02-12
申请号：JP2002203060
申请日：2002-07-11
申请人： Sumitomo Bakelite Co Ltd , 住友ベークライト株式会社
发明人： KAWAGUCHI HITOSHI
IPC分类号： H01L23/12 , H01L21/56 , H01L21/60
CPC分类号： H01L2224/13
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can cope with an acceleration of a speed of a semiconductor with a low cost and superior reliability, even when a wafer is increased in diameter by efficiently and surely connecting an i/o terminal of a semiconductor element to a circuit for re-wiring at a shortest distance. SOLUTION: In the semiconductor device, in which bonding pads, bond fingers and the circuit for re-wiring are disposed on each semiconductor chip on an insulating resin layer 3 formed over the entire surface of a semiconductor wafer formed with the semiconductor chip, the i/o terminal of the chip is connected to the circuit for the re-wiring via a stud bump 5 disposed on the terminal; and the wafer is divided into individual chips; the insulating resin layer is supplied in a state in which an insulating resin layer 3; and a metal layer 1 are formed on a resin base film 2. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了提供能够以低成本和优异的可靠性来应对半导体的速度的加速的半导体器件，即使通过有效地且可靠地连接i / o来增加晶圆的直径，将半导体元件的端子连接到用于以最短距离重新布线的电路。解决方案：在半导体器件中，在形成有半导体芯片的半导体晶片的整个表面上形成的绝缘树脂层3上的每个半导体芯片上设置有接合焊盘，接合指和再配线电路芯片的i / o端子通过设置在端子上的柱形突起5连接到用于重新布线的电路; 并将晶片分成单独的芯片; 绝缘树脂层以绝缘树脂层3的状态供给; 并且在树脂基底膜2上形成金属层1.版权所有（C）2004，JPO

7. 发明专利

JP2003347489A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2003347489A
公开(公告)日：2003-12-05
申请号：JP2002151832
申请日：2002-05-27
申请人： Sumitomo Bakelite Co Ltd , 住友ベークライト株式会社
发明人： KAWAGUCHI HITOSHI
IPC分类号： H01L23/40 , H01L23/36 , H01L23/373
摘要： PROBLEM TO BE SOLVED: To provide a method for effectively dissipating heat generated from a semiconductor element in the case that the semiconductor element is mounted on a substrate by using a flip chip method and packaged.
SOLUTION: In the method for manufacturing a semiconductor device, a columnar structure which is composed of a metal and penetrates an adhesive agent layer exists in the adhesive agent layer and is brought into contact with the semiconductor element or a sealing resin when a heat dissipating plate formed of metal is fixed, in a semiconductor device wherein the heat dissipating plate is fixed on the semiconductor element or the sealing resin by using an adhesive agent. It is preferable that the columnar structure is formed previously by using any one method out of a die casting method, an etching method and a plating method.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种在通过使用倒装芯片方法将半导体元件安装在基板上并且被封装的情况下，有效地散发由半导体元件产生的热量的方法。解决方案：在半导体器件的制造方法中，由粘合剂层构成由金属构成的贯通粘接剂层的柱状结构体，与粘接剂层接触时，与半导体元件或密封树脂接触时通过使用粘合剂将散热板固定在半导体元件或密封树脂上的半导体器件中固定由金属形成的散热板。优选通过使用压铸法，蚀刻法和电镀法中的任一种方法预先形成柱状结构。版权所有（C）2004，JPO

8. 发明专利

JP2007317943A Substrate, and semiconductor device 审中-公开
标题翻译：基板和半导体器件
公开(公告)号：JP2007317943A
公开(公告)日：2007-12-06
申请号：JP2006146974
申请日：2006-05-26
申请人： Sumitomo Bakelite Co Ltd , 住友ベークライト株式会社
发明人： ITO TEPPEI , KAWAGUCHI HITOSHI , TANAKA HIROYUKI
IPC分类号： H05K3/46 , H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a substrate which can reduce occurrence of warp, and to provide a semiconductor device using the substrate.
SOLUTION: A substrate 3 has a build-up layer wherein an insulating layer comprising resin and a conductor wiring layer 312 are laminated alternately and each conductor wiring layer 312 is connected by a conductor layer formed in the via hole of the insulation layer. A conductor wiring layer 312D disposed in a substrate outermost side of the conductor wiring layer 312 is formed in a signal wiring arrangement area A, and has a plurality of signal lines 312D1 extended in a prescribed direction. When a linear expansion coefficient is specified as (αsig-x) measured by a laser speckle method in an almost parallel direction of the signal line 312D1 of the signal line arrangement area A wherein the signal line 312D1 is disposed, and a linear expansion coefficient is specified as (αsig-y) by the speckle method in an almost orthogonal direction to the signal line 312D1, signal line direction dependency of a linear expansion coefficient ((αsig-y-αsig-x)/αsig-x)×100 is 25 or less.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供能够减少翘曲发生的基板，提供使用该基板的半导体装置。解决方案：衬底3具有堆叠层，其中包含树脂和导体布线层312的绝缘层交替层叠，并且每个导体布线层312通过形成在绝缘层的通孔中的导体层连接。布置在导体布线层312的基板最外侧的导体布线层312D形成在信号配线布置区域A中，并且具有沿预定方向延伸的多条信号线312D1。当通过激光散斑法在信号线布置区域A的信号线312D1的信号线312D1的大致平行方向上测量的信号线312D1的线性膨胀系数被指定为（αsig-x）时，线膨胀系数为在与信号线312D1几乎正交的方向上通过斑点法指定为（αsig-y），线膨胀系数（（αsig-y-αsig-x）/αsig-x）×100的信号线方向依赖性为25 或更少。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007177150A Epoxy resin composition and semiconductor device 有权
标题翻译：环氧树脂组合物和半导体器件
公开(公告)号：JP2007177150A
公开(公告)日：2007-07-12
申请号：JP2005379312
申请日：2005-12-28
申请人： Sumitomo Bakelite Co Ltd , 住友ベークライト株式会社
发明人： HIROSE HIROSHI , KAWAGUCHI HITOSHI , SASAJIMA HIDEAKI
IPC分类号： C08G59/62 , C08K3/00 , C08K3/24 , C08L63/00 , H01L23/29 , H01L23/31
摘要： PROBLEM TO BE SOLVED: To provide an epoxy resin composition which is used to encapsulate an area mounting type semiconductor, keeps itself in flame-retardance, and can suppress a semiconductor device from being warped at a temperature of -55°C to 260°C; and a semiconductor device using the same. SOLUTION: The epoxy resin composition comprises (A) at least one epoxy resin selected from following formulae (1), (2), (3), and (4); (B) at least one curing agent selected from following formulae (5), (6), (7), and (8); (C) an inorganic filler having an aspect ratio of 10-40; and (D) a flame-retardant. The area mounting type semiconductor device has a substrate substantially only the one surface of which is installed with semiconductor elements and encapsulated with the epoxy resin composition. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供用于封装区域安装型半导体的环氧树脂组合物，其自身保持阻燃性，并且可以抑制半导体器件在-55℃至 260℃; 以及使用该半导体装置的半导体装置。环氧树脂组合物包含（A）至少一种选自下式（1），（2），（3）和（4）的环氧树脂; （B）至少一种选自下述式（5），（6），（7）和（8）的固化剂; （C）长宽比为10-40的无机填料; 和（D）阻燃剂。区域安装型半导体器件具有基本上仅一个表面安装有半导体元件并且被环氧树脂组合物包封的基板。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2006216869A Composite substrate and its manufacturing method 审中-公开
标题翻译：复合基材及其制造方法
公开(公告)号：JP2006216869A
公开(公告)日：2006-08-17
申请号：JP2005029943
申请日：2005-02-07
申请人： Sumitomo Bakelite Co Ltd , 住友ベークライト株式会社
发明人： ISHIBASHI KATSUYUKI , KAWAGUCHI HITOSHI
IPC分类号： H05K1/14 , H05K3/36 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a composite wiring board which is excellent in layout efficiency, can be thinned with the high degree of freedom of design, and is excellent in connection reliability as well, and a manufacturing method of the composite wiring board which is excellent in an yield and capable of simplifying processes. SOLUTION: For the composite substrate, a flexible wiring board provided with a conductor part for interlayer connection and a module wiring board provided with a land for conductor joining are joined on one surface. The joining part is constituted of a joining part by an adhesive material layer and the conductor joining part of the conductor part for the interlayer connection of the flexible wiring board, and the land for the conductor joining of the module wiring board. The manufacturing method of the composite substrate comprises a process of laminating the flexible wiring board provided with a conductor circuit, an insulating layer and the conductor for the interlayer connection exposed through the insulating layer onto the conductor circuit, and the module wiring board provided with the land for the conductor joining through the adhesive material layer, so that the conductor part for the interlayer connection, and the land for the conductor joining face each other; and a process of executing the interlayer connection by heating and press fitting. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供布局效率优异的复合布线板，可以以高设计自由度进行薄化，并且连接可靠性也优异，并且复合布线的制造方法产量优良，能简化工艺的板材。解决方案：对于复合基板，设置有用于层间连接的导体部分的柔性布线板和设置有用于导体接合的焊盘的模块布线板在一个表面上接合。接合部分由粘合材料层的接合部分和用于柔性布线板的层间连接的导体部分的导体接合部分和用于模块布线板的导体接合的焊盘构成。复合基板的制造方法包括将设置有导体电路的柔性布线板，绝缘层和通过绝缘层露出的层间连接导体层叠在导体电路上的工序，导体通过粘合材料层接合，使得用于层间连接的导体部分和用于导体接合的焊盘面彼此面对; 以及通过加热和压配合执行层间连接的过程。版权所有（C）2006，JPO＆NCIPI

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