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1. 发明授权

US4494219A Nonvolatile read only memory device 失效
标题翻译：非易失性只读存储器件
公开(公告)号：US4494219A
公开(公告)日：1985-01-15
申请号：US344050
申请日：1982-01-29
申请人： Sumio Tanaka , Shigeyoshi Watanabe
发明人： Sumio Tanaka , Shigeyoshi Watanabe
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28 , G11C16/32 , G11C29/00 , G11C29/12 , G11C29/24 , G11C7/00
CPC分类号： G11C16/32 , G11C16/28
摘要： A nonvolatile read only memory detects a time varying change of the amount of data written in the memory cell transistor using a circuit for supplying a constant potential which is higher than the threshold voltage of a reference cell transistor and which is independent of a power source voltage used for reading out connected to the gate of the reference cell transistor.
摘要翻译：非易失性只读存储器使用用于提供高于参考单元晶体管的阈值电压的恒定电位的电路来检测写入存储单元晶体管的数据量的时变变化，并且其独立于电源电压用于读出连接到参考单元晶体管的栅极。

2. 发明授权

US4531202A Semiconductor nonvolatile read only memory device 失效
标题翻译：半导体非易失性只读存储器件
公开(公告)号：US4531202A
公开(公告)日：1985-07-23
申请号：US344049
申请日：1982-01-29
申请人： Shigeyoshi Watanabe , Sumio Tanaka
发明人： Shigeyoshi Watanabe , Sumio Tanaka
IPC分类号： G11C17/00 , G11C16/06 , G11C16/08 , G11C11/40
CPC分类号： G11C16/08
摘要： A semiconductor nonvolatile read only memory device has a voltage applying circuit which sets all word lines at ground potential in a stand-by mode and sets only a selected word line at a high level in an active mode. The word lines are connected to the gates of semiconductor nonvolatile memory transistors. Each of the memory transistors has the source (or drain) grounded and the drain (or source) connected to output lines. In a stand-by mode, the voltage applying circuit keeps all the word lines at ground potential. In an active mode, the voltage applying circuit applies a high level voltage only to the selected word line. The memory transistor connected to the selected word line produces data of "0" or "1" to the output line.
摘要翻译：半导体非易失性只读存储器件具有电压施加电路，其以待机模式将所有字线设置为接地电位，并且在活动模式中仅将所选择的字线设置为高电平。字线连接到半导体非易失性存储晶体管的栅极。每个存储晶体管的源极（或漏极）接地，漏极（或源极）连接到输出线。在待机模式下，电压施加电路使所有字线保持接地电位。在有源模式下，电压施加电路仅对所选择的字线施加高电平电压。连接到所选字线的存储晶体管对输出线产生“0”或“1”的数据。

3. 发明授权

US07295456B2 Chain ferroelectric random access memory (CFRAM) having an intrinsic transistor connected in parallel with a ferroelectric capacitor 有权
标题翻译：具有与铁电电容器并联连接的本征晶体管的链式铁电随机存取存储器（CFRAM）
公开(公告)号：US07295456B2
公开(公告)日：2007-11-13
申请号：US11382098
申请日：2006-05-08
申请人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
发明人： Ryu Ogiwara , Daisaburo Takashima , Sumio Tanaka , Yukihito Oowaki , Yoshiaki Takeuchi
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A chain type ferroelectric random access memory has a memory cell unit including ferroelectric memory cells electrically connected in series to each other, a plate line connected to an electrode of the memory cell unit, a bit line connected to the other electrode of the memory cell unit via a switching transistor, a sense amplifier which amplifies the voltages of this bit line and its complementary bit line, and a transistor inserted between the switching transistor and the sense amplifier. A value, being the minimum value of the gate voltage in the transistor obtained during elevation of the plate line voltage and comparative amplification, is smaller than a value, being the maximum value of the gate voltage in the transistor obtained during fall of the plate line voltage and comparative amplification. With these features, decrease in the accumulated charge of polarization in the memory cell is reduced and occurrence of disturb is prevented during read/write operations.
摘要翻译：链式铁电随机存取存储器具有包括彼此串联电连接的铁电存储单元的存储单元单元，连接到存储单元单元的电极的板线，连接到存储单元单元的另一个电极的位线通过开关晶体管，放大该位线及其互补位线的电压的读出放大器以及插在开关晶体管和读出放大器之间的晶体管。作为板线电压和比较放大的升压期间获得的晶体管中的栅极电压的最小值的值小于在板线掉电期间获得的晶体管中的栅极电压的最大值电压和比较放大。利用这些特征，存储单元中的累积电荷的减小减少，并且在读/写操作期间阻止了干扰的发生。

4. 发明授权

US6166987A Nonvolatile semiconductor memory device having row decoder 失效
标题翻译：具有行解码器的非易失性半导体存储器件
公开(公告)号：US6166987A
公开(公告)日：2000-12-26
申请号：US443100
申请日：1999-11-18
申请人： Shigeru Atsumi , Sumio Tanaka
发明人： Shigeru Atsumi , Sumio Tanaka
IPC分类号： G11C17/00 , G11C7/00 , G11C8/00 , G11C8/08 , G11C16/06 , G11C16/08 , G11C16/14 , H01L21/8247 , H01L27/10 , H01L27/115
CPC分类号： G11C8/08 , G11C16/08 , G11C16/14
摘要： A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.
摘要翻译：提供了一种非易失性半导体存储器件，其中在擦除模式期间将负电压施加到存储单元晶体管的栅电极。存储器件包括具有连接到字线的N沟道晶体管的行解码器电路。 N沟道晶体管设置在半导体衬底的P型阱区上。在擦除模式期间，向P型阱区施加负电压，而在其它模式期间施加接地电位。

5. 发明授权

US6111777A Ferroelectric memory 失效
标题翻译：铁电存储器
公开(公告)号：US6111777A
公开(公告)日：2000-08-29
申请号：US401663
申请日：1999-09-23
申请人： Ryu Ogiwara , Sumio Tanaka
发明人： Ryu Ogiwara , Sumio Tanaka
IPC分类号： G11C14/00 , G11C11/22 , H01L27/10
CPC分类号： G11C11/22
摘要： A dummy cell is provided in every column and consists of a dummy capacitor and two transistors. When the charge of the ferroelectric capacitor is released to one of a bit line pair, a first dummy word line is selected and charge of the dummy capacitor is released to the other of the bit line pair by way of one of the two transistors. When the charge of the ferroelectric capacitor is released to the other of the bit line pair, a second dummy word line is selected and the charge of the dummy capacitor is released to one of the bit line pair by way of the other one of the two transistors. When either one of the first and second dummy word lines is selected the dummy plate driver supplies a clock signal to the dummy capacitor.
摘要翻译：每个列提供一个虚拟单元，由虚拟电容器和两个晶体管构成。当铁电电容器的电荷被释放到位线对中的一个时，选择第一虚拟字线，并且通过两个晶体管之一将虚拟电容器的电荷释放到位线对中的另一个。当铁电电容器的电荷释放到位线对中的另一个时，选择第二虚拟字线，并且虚拟电容器的电荷通过两个位线对中的另一个被释放到位线对中的一个晶体管。当选择第一和第二虚拟字线中的任何一个时，虚拟板驱动器向虚拟电容器提供时钟信号。

6. 发明授权

US5875129A Nonvolatile semiconductor memory device including potential generating circuit 失效
标题翻译：包括电位发生电路的非易失性半导体存储器件
公开(公告)号：US5875129A
公开(公告)日：1999-02-23
申请号：US744821
申请日：1996-11-06
申请人： Shigeru Atsumi , Sumio Tanaka
发明人： Shigeru Atsumi , Sumio Tanaka
IPC分类号： H01L21/8247 , G11C16/08 , G11C16/30 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： G11C16/30 , G11C16/08 , H01L27/105
摘要： In a flash memory EEPROM, a memory cell MC is formed in a P-type semiconductor substrate. A peripheral transistor TR is formed in an N-type well. Another peripheral transistor TR is formed in a P-type well. The P-type well is by turn formed an N-type well and electrically insulated from the substrate. The substrate is typically provided with a metal back structure and its substrate voltage is set to predetermined voltages respectively for data erasure, data storage and data retrieval. With such an arrangement, the level of voltage stress with which the device is loaded during data erasure can be remarkably reduced to allow a down-sizing and an enhanced quality to be realized for the device.
摘要翻译：在闪速存储器EEPROM中，在P型半导体衬底中形成存储单元MC。外围晶体管TR形成在N型阱中。另一个外围晶体管TR形成在P型阱中。 P型阱依次形成N型阱并与衬底电绝缘。基板通常设置有金属背部结构，并且其基板电压分别设置为预定电压用于数据擦除，数据存储和数据检索。通过这样的布置，可以显着地减少在数据擦除期间装载装置的电压应力的水平，以允许对装置实现缩小尺寸和增强的质量。

7. 发明授权

US5265061A Apparatus for preventing glitch for semiconductor non-volatile memory device 失效
标题翻译：用于防止半导体非易失性存储器件毛刺的装置
公开(公告)号：US5265061A
公开(公告)日：1993-11-23
申请号：US943145
申请日：1992-09-10
申请人： Sumio Tanaka
发明人： Sumio Tanaka
IPC分类号： G11C7/14 , G11C17/12 , G11C7/00 , G11C11/40 , H03K19/003 , H03K19/0175
CPC分类号： G11C17/12 , G11C7/14
摘要： A semiconductor non-volatile memory device having non-volatile memory cells for storing binary data, a plurality of column lines respectively connected to the plurality of memory cells and a plurality of row lines respectively connected to the plurality of memory cells comprising a plurality of dummy cells, having the same structure as the memory cells, respectively connected to the column lines and arranged to be set in an ON state upon being selected, a dummy row line connected to the plurality of dummy cells, a dummy row line selector for selecting the dummy row line for a predetermined period in response to a chip selection signal for selecting the memory device. Therefore, since the dummy row line is selected for the predetermined period before the memory device is selected by a computer system or the like, each of the column lines is set at a ground potential by a dummy memory cell set in an ON state. During a transition from the non-selected state to a selected state of the memory device, in synchronism with the transition from the non-selected state to the selected state of a target memory cell in a plurality of memory cells, the state of a dummy cell connected to the target memory cell transits from the selected state to the non-selected state.
摘要翻译：一种具有用于存储二进制数据的非易失性存储单元的半导体非易失性存储器件，分别连接到多个存储器单元的多个列线以及分别连接到多个存储器单元的多个行线，包括多个虚拟单元，具有与存储单元相同的结构，分别连接到列线并被布置为在选择时被设置为ON状态，连接到多个虚设单元的虚拟行线，用于选择响应于用于选择存储器件的芯片选择信号，预定周期的虚拟行线。因此，由于在通过计算机系统等选择存储器件之前的预定时段内选择了虚拟行线，所以通过设置在ON状态的虚拟存储器单元将每条列线设置为接地电位。在从非选择状态到存储器件的选择状态的转变期间，与从多个存储器单元中的目标存储器单元从未选择状态到选定状态的转换同步，虚拟的状态连接到目标存储器单元的单元从所选状态转换到未选择状态。

8. 发明授权

US5237534A Data sense circuit for a semiconductor nonvolatile memory device 失效
标题翻译：用于半导体非易失性存储器件的数据检测电路
公开(公告)号：US5237534A
公开(公告)日：1993-08-17
申请号：US854793
申请日：1992-03-23
申请人： Sumio Tanaka , Toshiyuki Sanko
发明人： Sumio Tanaka , Toshiyuki Sanko
IPC分类号： G11C16/04 , G11C16/28
CPC分类号： G11C16/0441 , G11C16/28
摘要： The current paths of column selection transistors are inserted between a pair of input nodes, on the one hand, of a sense amplifier constituted by a current-mirror type differential amplifier, and column lines, on the other hand. The current paths of transistors for clamping column potential are inserted between the input nodes of the sense amplifier, on the one hand, and a power source, on the other. The gates of the transistors for clamping column potential are supplied with a bias potential lower than the potential of the power source. When data is read out from selected memory cells, the potential of the input nodes of the sense amplifier is clamped to a value lower than the potential Vcc of the power source by the transistors for clamping column potential. The storage data in the selected memory cells is input directly to the input nodes of the sense amplifier through the current paths of the column selection transistors.
摘要翻译：另一方面，列选择晶体管的电流路径插入在一对输入节点之间，一方面由电流镜型差分放大器构成的读出放大器和列线。用于钳位列电势的晶体管的电流路径一方面插入在读出放大器的输入节点和另一端的电源之间。用于钳位列电位的晶体管的栅极被提供有低于电源电位的偏置电位。当从所选择的存储单元中读出数据时，读出放大器的输入节点的电位被钳位在用于钳位列电位的晶体管的电压低于电源的电位Vcc。所选存储单元中的存储数据通过列选择晶体管的电流路径直接输入到读出放大器的输入节点。

9. 发明授权

US4956816A Non-volatile semiconductor memory having improved testing circuitry 失效
标题翻译：具有改进测试电路的非易失性半导体存储器
公开(公告)号：US4956816A
公开(公告)日：1990-09-11
申请号：US358482
申请日：1989-05-30
申请人： Shigeru Atsumi , Sumio Tanaka , Shinji Saito , Nobuaki Otsuka
发明人： Shigeru Atsumi , Sumio Tanaka , Shinji Saito , Nobuaki Otsuka
IPC分类号： G11C17/00 , G11C16/34 , G11C29/00 , G11C29/06 , G11C29/50
CPC分类号： G11C29/50004 , G11C16/34 , G11C29/50 , G11C29/50016 , G06F2201/81 , G11C16/04
摘要： This invention provides a non-volatile semiconductor memory having a first node and a second node, the second node having a ground potential. The invention includes a plurality of non-volatile memory cells each having a drain and a threshold potential, the cells, for storing data written into the cells at a predetermined normal writing voltage. A plurality of bit lines, each memory cell being connected to one of the bit lines, transfer data to and from the memory cells. A circuit connected to the bit lines simultaneously tests the memory cells of all the bit lines at the normal writing voltage to detect changes in the threshold potential.
摘要翻译：本发明提供一种具有第一节点和第二节点的非易失性半导体存储器，第二节点具有接地电位。本发明包括多个具有漏极和阈值电位的非易失性存储单元，用于存储以预定的正常写入电压写入单元的数据。多个位线，每个存储单元连接到一个位线，将数据传送到存储单元和从存储单元传送数据。连接到位线的电路同时以正常写入电压测试所有位线的存储单元，以检测阈值电位的变化。

10. 发明授权

US4893275A High voltage switching circuit in a nonvolatile memory 失效
标题翻译：非易失性存储器中的高压开关电路
公开(公告)号：US4893275A
公开(公告)日：1990-01-09
申请号：US173563
申请日：1988-03-25
申请人： Sumio Tanaka , Shigeru Atsumi , Nobuaki Ohtsuka , Keniti Imamiya
发明人： Sumio Tanaka , Shigeru Atsumi , Nobuaki Ohtsuka , Keniti Imamiya
IPC分类号： G11C17/00 , G11C16/06 , G11C16/12 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L29/788 , H01L29/792 , H03K17/693
CPC分类号： G11C16/12
摘要： A nonvolatile semiconductor memory device includes a power voltage select circuit that is comprised of first and second power source nodes, an output node, first and second depletion type MOS transistors connected in series between the first power source node and the output node, a third MOS transistor connected between an interconnection point between the first and second depletion type MOS transistors and the second power source node, and a fourth MOS transistor connected between the second power source node and the output node.
摘要翻译：非易失性半导体存储器件包括由第一和第二电源节点组成的电源电压选择电路，串联连接在第一电源节点和输出节点之间的输出节点，第一和第二耗尽型MOS晶体管，第三MOS 连接在第一和第二耗尽型MOS晶体管与第二电源节点之间的互连点之间的晶体管，以及连接在第二电源节点和输出节点之间的第四MOS晶体管。

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