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1. 发明授权

US08129778B2 Semiconductor devices and methods for making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08129778B2
公开(公告)日：2012-03-06
申请号：US12629232
申请日：2009-12-02
申请人： Suku Kim , James J. Murphy , Gary Dolny
发明人： Suku Kim , James J. Murphy , Gary Dolny
IPC分类号： H01L21/00
CPC分类号： H01L29/8083 , H01L29/0634 , H01L29/1066 , H01L29/7722
摘要： Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.
摘要翻译：描述了用于制造这种特别适用于高频应用的器件的半导体器件和方法。半导体器件将SIT（或结型场效应晶体管[JFET]）结构与PN超结结构相结合。 SIT结构可以使用包含夹在厚介电层之间的栅极的沟槽形成。当栅极垂直夹在沟槽中的两个隔离区域之间时，其也连接到一个导电类型的超结结构的区域，从而允许控制半导体器件的电流路径。这种半导体器件相对于传统的平面栅极和凹入栅极SIT半导体器件具有较低的电阻率和电容。描述其他实施例。

2. 发明申请

US20110127601A1 Semiconductor Devices and Methods for Making the Same 有权
标题翻译：半导体器件及其制作方法
公开(公告)号：US20110127601A1
公开(公告)日：2011-06-02
申请号：US12629232
申请日：2009-12-02
申请人： Suku Kim , James J. Murphy , Gary Dolny
发明人： Suku Kim , James J. Murphy , Gary Dolny
IPC分类号： H01L29/78
CPC分类号： H01L29/8083 , H01L29/0634 , H01L29/1066 , H01L29/7722
摘要： Semiconductor devices and methods for making such devices that are especially suited for high-frequency applications are described. The semiconductor devices combine a SIT (or a junction field-effect transistor [JFET]) architecture with a PN super-junction structure. The SIT architecture can be made using a trench formation containing a gate that is sandwiched between thick dielectric layers. While the gate is vertically sandwiched between the two isolating regions in the trench, it is also connected to a region of one conductivity type of the super-junction structure, thereby allowing control of the current path of the semiconductor device. Such semiconductor devices have a lower specific resistance and capacitance relative to conventional planar gate and recessed gate SIT semiconductor devices. Other embodiments are described.
摘要翻译：描述了用于制造这种特别适用于高频应用的器件的半导体器件和方法。半导体器件将SIT（或结型场效应晶体管[JFET]）结构与PN超结结构相结合。 SIT结构可以使用包含夹在厚介电层之间的栅极的沟槽形成。当栅极垂直夹在沟槽中的两个隔离区域之间时，其也连接到一个导电类型的超结结构的区域，从而允许控制半导体器件的电流路径。这种半导体器件相对于传统的平面栅极和凹入栅极SIT半导体器件具有较低的电阻率和电容。描述其他实施例。

3. 发明授权

US08058732B2 Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same 失效
标题翻译：用于晶圆级芯片尺寸封装的半导体晶片结构，用于使用它们的功率器件，封装和系统及其制造方法
公开(公告)号：US08058732B2
公开(公告)日：2011-11-15
申请号：US12275086
申请日：2008-11-20
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Ihsiu Ho , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Rohit Dikshit
IPC分类号： H01L23/48
CPC分类号： H01L29/7802 , H01L23/3114 , H01L23/36 , H01L23/482 , H01L24/16 , H01L24/19 , H01L24/31 , H01L29/0657 , H01L2224/04105 , H01L2224/20 , H01L2224/73253 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/1461 , H01L2924/351 , H01L2924/00
摘要： Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.
摘要翻译：公开了半导体管芯结构，其使具有垂直功率器件的管芯封装在晶片级芯片级封装中，其中导电端子存在于管芯的一个表面处，并且器件具有非常低的导通状态抵抗性。在示例性实施例中，沟槽和孔形成在管芯的背面，孔与导管的顶表面处的导电区接触。可以在沟槽和孔上设置导电层和/或导体，以将器件的背面导电电极电耦合到导电区域。还公开了使用根据本发明的具有模具结构的模具的封装和系统，以及根据本发明的具有模具结构的模具的方法。

4. 发明申请

US20090273082A1 METHODS AND DESIGNS FOR LOCALIZED WAFER THINNING 有权
标题翻译：本地化方法和设计方法
公开(公告)号：US20090273082A1
公开(公告)日：2009-11-05
申请号：US12115254
申请日：2008-05-05
申请人： Suku Kim , James J. Murphy , Michael D. Gruenhagen , Matthew R. Reynolds , Romel N. Manatad , Jan Vincent Mancelita
发明人： Suku Kim , James J. Murphy , Michael D. Gruenhagen , Matthew R. Reynolds , Romel N. Manatad , Jan Vincent Mancelita
IPC分类号： H01L23/488 , H01L21/768
CPC分类号： H01L21/74 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05 , H01L2224/16 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
摘要翻译：描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。双向图案设计保持通道不与晶片的晶体取向对齐。然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。还描述了其它实施例。

5. 发明申请

US20090181520A1 Method and Structure for Dividing a Substrate into Individual Devices 有权
标题翻译：将基板划分为单个设备的方法和结构
公开(公告)号：US20090181520A1
公开(公告)日：2009-07-16
申请号：US12174863
申请日：2008-07-17
申请人： Minhua Li , Qi Wang , Gordon Sim , Matthew Reynolds , Suku Kim , James J. Murphy , Hamza Yilmaz
发明人： Minhua Li , Qi Wang , Gordon Sim , Matthew Reynolds , Suku Kim , James J. Murphy , Hamza Yilmaz
IPC分类号： H01L21/78
CPC分类号： H01L21/78
摘要： A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.
摘要翻译：公开了一种从半导体结构获得单个管芯的方法。半导体结构包括器件层，器件层又包括由预定间隔隔开的有源区。在器件层的背侧选择性地形成厚金属，使得在有源区的背面形成厚金属，而不在预定间隔的背面形成厚金属。然后沿着预定的间隔切割半导体结构，以将其背面的厚金属的活性区域分离成单独的管芯。

6. 发明授权

US08598035B2 Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same 有权
标题翻译：具有填充弹性材料的后侧沟槽的半导体裸片，用于改善附着，使用其的封装及其制造方法
公开(公告)号：US08598035B2
公开(公告)日：2013-12-03
申请号：US13151495
申请日：2011-06-02
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L21/44
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

7. 发明申请

US20120168947A1 Methods and Designs for Localized Wafer Thinning 有权
标题翻译：局部晶圆薄化的方法与设计
公开(公告)号：US20120168947A1
公开(公告)日：2012-07-05
申请号：US13404317
申请日：2012-02-24
申请人： Suku Kim , James J. Murphy , Michael D. Gruenhagen , Matthew R. Reynolds , Romel N. Manatad , Jan Vincent C. Mancelita
发明人： Suku Kim , James J. Murphy , Michael D. Gruenhagen , Matthew R. Reynolds , Romel N. Manatad , Jan Vincent C. Mancelita
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L21/74 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05 , H01L2224/16 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1301 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.
摘要翻译：描述了半导体器件中使用的晶片的局部变薄方法和由这些方法形成的结构。该方法使半导体晶片的背面薄的局部区域形成具有在晶片（或管芯）内重复的双向通道设计的凹槽，使得没有直通道线穿过晶片（或管芯）。双向图案设计保持通道不与晶片的晶体取向对齐。然后通过将适当尺寸的焊球落入凹槽中然后通过焊球落下工艺填充凹陷，然后退火晶片以回流焊球并使其平坦化。回流工艺开始从底部向上填充凹槽，从而避免了空隙形成和回流焊料中形成的空气阱。还描述了其它实施例。

8. 发明申请

US20110230046A1 SEMICONDUCTOR DICE WITH BACKSIDE TRENCHES FILLED WITH ELASTIC MATERIAL FOR IMPROVED ATTACHMENT, PACKAGES USING THE SAME, AND METHODS OF MAKING THE SAME 有权
标题翻译：具有用于改进附件的用弹性材料填充的背面斜面的半导体切片，使用其的包装及其制造方法
公开(公告)号：US20110230046A1
公开(公告)日：2011-09-22
申请号：US13151495
申请日：2011-06-02
申请人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
发明人： Michael D. Gruenhagen , Suku Kim , James J. Murphy , Eddy Tjhia , Chung-Lin Wu , Mark Larsen , Douglas E. Dolan
IPC分类号： H01L21/28
CPC分类号： H01L23/49513 , H01L23/49524 , H01L24/05 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L29/0657 , H01L2224/0401 , H01L2224/04026 , H01L2224/04042 , H01L2224/05555 , H01L2224/05556 , H01L2224/13099 , H01L2224/16 , H01L2224/2518 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73255 , H01L2224/73265 , H01L2224/83856 , H01L2224/92247 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10158 , H01L2924/10253 , H01L2924/13091 , H01L2924/351 , H01L2924/00 , H01L2924/0105 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599 , H01L2224/37099
摘要： Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
摘要翻译：公开了具有填充有弹性导电材料的背面沟槽的半导体裸片。沟槽减小了掺入骰子的器件的导通电阻。弹性导电材料为模具的背面提供导电路径，在半导体芯片上由热循环引起的微小应力。还公开了使用骰子的包裹以及制造骰子的方法。

9. 发明申请

US20110201179A1 METHOD AND STRUCTURE FOR DIVIDING A SUBSTRATE INTO INDIVIDUAL DEVICES 有权
标题翻译：将基板分解成个体设备的方法和结构
公开(公告)号：US20110201179A1
公开(公告)日：2011-08-18
申请号：US13095584
申请日：2011-04-27
申请人： Minhua Li , Qi Wang , Gordon Sim , Matthew Reynolds , Suku Kim , James J. Murphy , Hamza Yilmaz
发明人： Minhua Li , Qi Wang , Gordon Sim , Matthew Reynolds , Suku Kim , James J. Murphy , Hamza Yilmaz
IPC分类号： H01L21/78
CPC分类号： H01L21/78
摘要： A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.
摘要翻译：公开了一种从半导体结构获得单个管芯的方法。半导体结构包括器件层，器件层又包括由预定间隔隔开的有源区。在器件层的背侧选择性地形成厚金属，使得在有源区的背面形成厚金属，而不在预定间隔的背面形成厚金属。然后沿着预定的间隔切割半导体结构，以将其背面的厚金属的活性区域分离成单独的管芯。

10. 发明申请

US20110031596A1 NICKEL-TITANUM SOLDERING LAYERS IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：半导体器件中的镍 - 锡焊料层
公开(公告)号：US20110031596A1
公开(公告)日：2011-02-10
申请号：US12535963
申请日：2009-08-05
申请人： Mike D. Gruenhagen , James J. Murphy , Suku Kim , Jim Pierce , William S. Beggs , Thomas P. Welch
发明人： Mike D. Gruenhagen , James J. Murphy , Suku Kim , Jim Pierce , William S. Beggs , Thomas P. Welch
IPC分类号： H01L23/495 , H01L23/498 , H01L23/488 , B23K35/22
CPC分类号： B23K35/0238 , B23K35/262 , B23K35/3033 , B23K35/325 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/04026 , H01L2224/05155 , H01L2224/05166 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05664 , H01L2224/11318 , H01L2224/1132 , H01L2224/11334 , H01L2224/11462 , H01L2224/13111 , H01L2224/13116 , H01L2224/14181 , H01L2224/16245 , H01L2224/16503 , H01L2224/29111 , H01L2224/29116 , H01L2224/32245 , H01L2224/32503 , H01L2224/73153 , H01L2224/73253 , H01L2224/81191 , H01L2224/81815 , H01L2224/83191 , H01L2224/83815 , H01L2224/9221 , H01L2224/94 , H01L2924/00013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/01322 , H01L2924/01327 , H01L2924/04941 , H01L2924/12032 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/3512 , Y10T428/12222 , H01L2924/00014 , H01L2924/01022 , H01L2924/01028 , H01L2224/03 , H01L2924/0105 , H01L2924/01051 , H01L2924/01047 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds or alloys and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit, a contact layer contacting the substrate, a TiNi-containing soldering layer on the contact layer, an oxidation prevention layer on the soldering layer, a solder bump on the soldering layer, and a lead frame or PCB attached to the solder bump. The combination of the Ti and Ni materials in the soldering layer exhibits many features not found in the Ti and Ni materials alone, such as reduced wafer warpage, increased ductility for improved elasticity, decreased consumption of the Ni in the soldering layer, and decreased manufacturing costs. Other embodiments are described.
摘要翻译：描述了包含镍钛（NiTi或TiNi）化合物或合金的半导体器件及其制造方法。这些器件包含具有集成电路的硅衬底，与衬底接触的接触层，接触层上的含TiNi的焊接层，焊接层上的氧化防止层，焊接层上的焊料凸块和引线框架或PCB连接到焊料凸块。 Ti和Ni材料在焊接层中的组合在单独的Ti和Ni材料中显示出许多特征，例如减少晶片翘曲，提高延展性以改善弹性，降低焊接层中的Ni消耗以及减少制造费用描述其他实施例。

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