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1. 发明申请

US20130117636A1 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS 审中-公开
标题翻译：具有冗余电池的半导体存储器件和系统
公开(公告)号：US20130117636A1
公开(公告)日：2013-05-09
申请号：US13670822
申请日：2012-11-07
申请人： Su-a KIM , Dae-hyun KIM , Woo-jin LEE
发明人： Su-a KIM , Dae-hyun KIM , Woo-jin LEE
IPC分类号： G11C29/04 , G06F11/16
CPC分类号： G11C29/04 , G11C7/1045 , G11C29/808 , G11C29/81 , G11C29/848
摘要： In one embodiment, the memory device includes a memory cell array, a data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.
摘要翻译：在一个实施例中，存储器件包括存储单元阵列，数据线选择电路和选择控制逻辑。存储单元阵列具有至少第一存储单元组和冗余存储单元组。第一存储单元组包括与第一数据线相关联的多个第一存储单元，并且冗余存储单元组包括与冗余数据线相关联的多个冗余存储单元。所述选择控制逻辑被配置为检测所述第一存储器单元组中的有缺陷的存储单元是否被访问，并且被配置为控制所述数据线选择电路经由所述冗余数据线经由所述第一数据线的访问来替换访问，使得第一存储单元组中的检测到的有缺陷的存储单元被多个冗余存储单元中的一个代替。

2. 发明申请

US20130117615A1 SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS 审中-公开
标题翻译：具有冗余电池的半导体存储器件和系统
公开(公告)号：US20130117615A1
公开(公告)日：2013-05-09
申请号：US13671261
申请日：2012-11-07
申请人： Su-a KIM , Dae-hyun KIM , Woo-jin LEE
发明人： Su-a KIM , Dae-hyun KIM , Woo-jin LEE
IPC分类号： G11C29/04
CPC分类号： G11C29/04 , G11C7/1045 , G11C29/808 , G11C29/81 , G11C29/848
摘要： In one embodiment, the memory device includes a memory cell array, to data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells.
摘要翻译：在一个实施例中，存储器件包括存储单元阵列，数据线选择电路和选择控制逻辑。存储单元阵列具有至少第一存储单元组和冗余存储单元组。第一存储单元组包括与第一数据线相关联的多个第一存储单元，并且冗余存储单元组包括与冗余数据线相关联的多个冗余存储单元。所述选择控制逻辑被配置为检测所述第一存储器单元组中的有缺陷的存储单元是否被访问，并且被配置为控制所述数据线选择电路经由所述冗余数据线经由所述第一数据线的访问来替换访问，使得第一存储单元组中的检测到的有缺陷的存储单元被多个冗余存储单元中的一个代替。

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