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1. 发明授权

US07989911B1 Shallow trench isolation (STI) with trench liner of increased thickness 有权
标题翻译：浅沟槽隔离（STI），沟槽衬垫厚度增加
公开(公告)号：US07989911B1
公开(公告)日：2011-08-02
申请号：US12607868
申请日：2009-10-28
申请人： Sunil Mehta , Stewart Logie , Steven Fong
发明人： Sunil Mehta , Stewart Logie , Steven Fong
IPC分类号： H01L21/70
CPC分类号： H01L21/76224
摘要： In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and adjacent to the low voltage transistor regions, and a third trench between the first and second trenches and between and adjacent to a high voltage transistor region and a low voltage transistor region. A thicker silicon dioxide layer lines the first trench and a first portion of the third trench adjacent to a high voltage transistor region. A thinner silicon dioxide layer lines the second trench and a second portion of the third trench adjacent to a low voltage transistor region. A silicon nitride layer is present on the thinner silicon dioxide layer and lines the second trench and the second portion of the third trench but is not present on the thicker silicon dioxide layer and does not line the first trench and the first portion of the third trench.
摘要翻译：在一个实施例中，集成电路包括具有高电压晶体管区域和低压晶体管区域的衬底。衬底包括在高电压晶体管区域之间和之间相邻的第一沟槽，在低电压晶体管区域之间和之间的第二沟槽，以及在第一和第二沟槽之间并且在高压晶体管区域之间和之间的第三沟槽，以及低压晶体管区域。较厚的二氧化硅层将第一沟槽和第三沟槽的与高压晶体管区域相邻的第一部分排列。更薄的二氧化硅层将第二沟槽和第三沟槽的与低压晶体管区域相邻的第二部分排列。氮化硅层存在于较薄的二氧化硅层上，并且使第二沟槽和第三沟槽的第二部分排列，但是不存在于较厚的二氧化硅层上，并且不使第一沟槽和第三沟槽的第一部分。

2. 发明授权

US07985656B1 Shallow trench isolation (STI) with trench liner of increased thickness 有权
标题翻译：浅沟槽隔离（STI），沟槽衬垫厚度增加
公开(公告)号：US07985656B1
公开(公告)日：2011-07-26
申请号：US12607333
申请日：2009-10-28
申请人： Sunil Mehta , Stewart Logie , Steven Fong
发明人： Sunil Mehta , Stewart Logie , Steven Fong
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of manufacturing an integrated circuit includes etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage regions of the substrate. The substrate is then oxidized to form a silicon dioxide layer lining the first and second trenches, the layer having a first thickness. A silicon nitride layer is deposited on the silicon dioxide layer in the first and second trenches. The silicon nitride layer is then etched from the first trench but not from the second trench, thereby exposing the silicon layer in the first trench but not the second trench. The exposed silicon dioxide layer in the first trench is oxidized to increase the thickness of the silicon dioxide layer to a second thickness greater than the first thickness of the unexposed silicon dioxide layer in the second trench. The first and second trenches are then filled with a dielectric material.
摘要翻译：一种制造集成电路的方法包括蚀刻衬底以同时产生衬底的高电压晶体管区域和衬底的低电压区域之间的第二沟槽之间的第一沟槽。然后将衬底氧化以形成衬在第一和第二沟槽上的二氧化硅层，该层具有第一厚度。氮化硅层沉积在第一和第二沟槽中的二氧化硅层上。然后从第一沟槽蚀刻氮化硅层，但不从第二沟槽蚀刻氮化硅层，从而暴露第一沟槽中的硅层而不是第二沟槽。第一沟槽中暴露的二氧化硅层被氧化，以将二氧化硅层的厚度增加到大于第二沟槽中未曝光的二氧化硅层的第一厚度的第二厚度。然后用介电材料填充第一和第二沟槽。

3. 发明授权

US06570212B1 Complementary avalanche injection EEPROM cell 失效
标题翻译：互补雪崩注入EEPROM单元
公开(公告)号：US06570212B1
公开(公告)日：2003-05-27
申请号：US09578086
申请日：2000-05-24
申请人： Sunil D. Mehta , Steven Fong , Stewart Logie
发明人： Sunil D. Mehta , Steven Fong , Stewart Logie
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , G11C16/0441 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11529 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell at least partially formed in a semiconductor substrate, comprising a first avalanche injection element having a first active region of a first conductivity type and a second active region of a second conductivity type, separated by a channel region of said second conductivity type; a second avalanche injection element having a third active region of said second conductivity type and sharing said second active region with said first avalanche injection element, the second avalanche injection element having a channel region of said first conductivity type; and a common floating gate at least partially overlying said first and second avalanche injection elements. In a further embodiment, the first avalanche element has an N+/P junction, the second avalanche element has a P+/N junction, and the floating gate capacitively coupled to the first and second avalanche elements.
摘要翻译：至少部分地形成在半导体衬底中的非易失性存储单元，包括具有第一导电类型的第一有源区和第二导电类型的第二有源区的第一雪崩注入元件，由所述第二导电类型的沟道区分隔开导电型; 第二雪崩注入元件，具有所述第二导电类型的第三有源区，并且与所述第一雪崩注入元件共享所述第二有源区，所述第二雪崩注入元件具有所述第一导电类型的沟道区; 以及至少部分地覆盖所述第一和第二雪崩注入元件的公共浮动栅极。在另一实施例中，第一雪崩元件具有N + / P结，第二雪崩元件具有P + / N结，并且浮动栅极电容耦合到第一和第二雪崩元件。

4. 发明申请

US20060128162A1 Process for fabricating a semiconductor device having an RTCVD layer 审中-公开
标题翻译：制造具有RTCVD层的半导体器件的工艺
公开(公告)号：US20060128162A1
公开(公告)日：2006-06-15
申请号：US11013240
申请日：2004-12-14
申请人： Sunil Mehta , Steven Fong , YongZhong Hu
发明人： Sunil Mehta , Steven Fong , YongZhong Hu
IPC分类号： H01L21/31
CPC分类号： H01L21/0217 , C23C16/345 , H01L21/02271 , H01L21/3185
摘要： A process of fabricating a semiconductor device includes forming a device region including a non-volatile memory element and forming a utility layer overlying the device region, where the utility layer is a dielectric material formed by RTCVD. The utility layer preferably has a hydrogen content below that necessary to reduce the data retention of the non-volatile memory element in the device region. The utility layer can function as one or more of an etch-stop layer, a diffusion barrier layer, or an insulating layer.
摘要翻译：制造半导体器件的工艺包括形成包括非易失性存储元件的器件区域，并且形成覆盖器件区域的实用层，其中该实用层是由RTCVD形成的电介质材料。实用层优选具有低于在装置区域中减少非易失性存储元件的数据保持所需的氢含量。实用层可以用作蚀刻停止层，扩散阻挡层或绝缘层中的一个或多个。

5. 发明申请

US20070032789A1 Integrated three-port receptacle and method for connecting hand and foot switched electrosurgical accessories 失效
标题翻译：一体化三端口插座和手电连接电外科附件连接方法
公开(公告)号：US20070032789A1
公开(公告)日：2007-02-08
申请号：US11195976
申请日：2005-08-03
申请人： Wayne Gonnering , Steven Fong , Sunil Mehta
发明人： Wayne Gonnering , Steven Fong , Sunil Mehta
IPC分类号： A61B18/14
CPC分类号： A61B18/14 , A61B18/1206 , A61B2018/00178 , Y10S439/909
摘要： A three-port receptacle connects both single-prong and three-prong electrical connectors of electrosurgical accessories to an electrosurgical generator. The receptacle includes two control ports for accepting the two control prongs of the three-prong connector and an energy-delivery port for accepting the energy-conducting prong of the three-prong connector. The energy-delivery port also receives an energy-conducting prong of a single-prong connector. A single contact assembly is located behind the energy-delivery port and delivers electrosurgical power to the energy-conducting prongs of both types of accessory connectors.
摘要翻译：三口插座将电外科辅助部件的单管脚和三管电连接器连接到电外科发生器。插座包括两个控制端口，用于接收三插头连接器的两个控制插头和用于接受三插头连接器的导电插脚的能量输送端口。能量输送端口还接收单管连接器的导电插脚。单个接触组件位于能量输送端口后面，并将电外科电力传送到两种类型的附件连接器的导电插脚。

6. 发明申请

US20060145238A1 Diode structure for word-line protection in a memory circuit 审中-公开
标题翻译：存储器电路中字线保护的二极管结构
公开(公告)号：US20060145238A1
公开(公告)日：2006-07-06
申请号：US11029950
申请日：2005-01-05
申请人： Fabiano Fontana , Steven Fong , Sunil Mehta , Yongzhong Hu
发明人： Fabiano Fontana , Steven Fong , Sunil Mehta , Yongzhong Hu
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , G11C16/04 , H01L27/0255
摘要： One embodiment of the invention is an integrated circuit having: (i) an array of flash transistors formed on a substrate and arranged in one or more rows, each flash transistor having a control gate, wherein, in each row, the control gates are connected to a word line; and (ii) for each word line, at least one diode structure formed on the substrate and having first and second diodes, each diode having a cathode and an anode, wherein the word line is connected to the cathode of the first diode and to the anode of the second diode.
摘要翻译：本发明的一个实施例是一种集成电路，其具有：（i）形成在衬底上并布置成一行或多行的闪存晶体管阵列，每个闪存晶体管具有控制栅极，其中在每行中连接控制栅极到字线和（ii）对于每个字线，形成在所述衬底上并具有第一和第二二极管的至少一个二极管结构，每个二极管具有阴极和阳极，其中所述字线连接到所述第一二极管的阴极和第二二极管的阳极。

7. 发明授权

US08040124B2 Method and apparatus for monitoring leakage current of a faraday cup 有权
标题翻译：用于监测法拉第杯漏电流的方法和装置
公开(公告)号：US08040124B2
公开(公告)日：2011-10-18
申请号：US12388456
申请日：2009-02-18
申请人： Don Berrian , Steven Fong
发明人： Don Berrian , Steven Fong
IPC分类号： G01R19/00
CPC分类号： H01J37/3171 , G01R31/025 , H01J37/244 , H01J2237/022 , H01J2237/24405 , H01J2237/24507
摘要： A current branch circuit is electrically coupled with a Faraday cup and an operation amplifier separately. The Faraday cup, the current branch circuit and the operation amplifier are formed as a portion of an ion implanter. When the Faraday cup is electrically coupled with a ground through a conductive structure formed by an ion beam received by the Faraday cup, a current flows from the output of the operation amplifier to the current branch circuit to balance another current flow from the current branch circuit through the Faraday cup to the ground. By dynamically monitoring the voltage of the output of the operation amplifier, current flows through the Faraday cup to the ground and through the resistance of the conductive structure can be dynamically monitored. Accordingly, the difference between the ion current measured by the Faraday cup and the real ion current implanted to the wafer can be dynamically acquired to avoid overdosage of the wafer with the ion beam.
摘要翻译：电流分支电路分别与法拉第杯和运算放大器电耦合。法拉第杯，当前的分支电路和运算放大器形成为离子注入机的一部分。当法拉第杯通过由法拉第杯接收的离子束形成的导电结构与地面电耦合时，电流从运算放大器的输出流向电流分支电路，以平衡来自当前分支电路的另一电流通过法拉第杯到地面。通过动态监测运算放大器输出的电压，电流流经法拉第杯到达地面，通过导电结构的电阻可以动态监测。因此，可以动态地获取由法拉第杯测量的离子电流与植入晶片的实际离子电流之间的差异，以避免晶片与离子束的过量剂量。

8. 发明授权

US4960727A Method for forming a dielectric filled trench 失效
标题翻译：形成电介质填充沟槽的方法
公开(公告)号：US4960727A
公开(公告)日：1990-10-02
申请号：US274512
申请日：1988-11-18
申请人： Robert Mattox , Steven Fong
发明人： Robert Mattox , Steven Fong
IPC分类号： H01L21/314 , H01L21/762
CPC分类号： H01L21/3144 , H01L21/76224
摘要： A structure and method for forming an isolation wall in an etched trench are described. The trench walls are covered by a thin silicon oxide layer and the trench conformally filled with an oxy-nitride mixture having a particular range of composition so as to produce a neutral to slight tensile stress in the oxy-nitride relative to silicon. The structure is very simple to fabricate and creates fewer defects in the silicon substrate than prior art techniques. Buried voids in the filled trench are eliminated.
摘要翻译：描述了在蚀刻沟槽中形成隔离壁的结构和方法。沟槽壁被薄的氧化硅层覆盖，并且沟槽保形地填充有具有特定范围的组成的氮氧化物混合物，以便相对于硅在氮氧化物中产生中性至轻微的拉伸应力。与现有技术相比，该结构非常简单地制造并且在硅衬底中产生较少的缺陷。消除了在填充的沟槽中的埋入空隙。

9. 发明授权

US08315266B1 Extending a local area network 有权
标题翻译：扩展局域网
公开(公告)号：US08315266B1
公开(公告)日：2012-11-20
申请号：US13411172
申请日：2012-03-02
申请人： Cedric Fung Lam , Tony Ong , Ke Dong , Steven Fong , Yut Loy Chan , Yifan Gao , Milo Steven Medin , Dov Shimon Zimring
发明人： Cedric Fung Lam , Tony Ong , Ke Dong , Steven Fong , Yut Loy Chan , Yifan Gao , Milo Steven Medin , Dov Shimon Zimring
IPC分类号： H04L12/28
CPC分类号： H04L12/2834 , H04J2203/0001 , H04J2203/0003 , H04L12/2856 , H04L12/2898 , H04L12/66 , H04L29/0621 , H04L2012/2841
摘要： A set top box including a network extender and a media player in communication with the network extender. The network extender is connectable to a residential gateway of a local area network through a wired connection. The media player includes a computing processor executing instructions to format a signal received from the network extender for use by a media device. The set top box also includes at least one wireless transceiver in communication with the network extender.
摘要翻译：机顶盒包括网络扩展器和与网络扩展器通信的媒体播放器。网络扩展器可以通过有线连接连接到局域网的住宅网关。媒体播放器包括执行指令以格式化从网络扩展器接收的信号以供媒体设备使用的计算处理器。机顶盒还包括与网络扩展器通信的至少一个无线收发器。

10. 发明申请

US20070030736A1 Variable source resistor for flash memory 审中-公开
标题翻译：闪存可变源电阻
公开(公告)号：US20070030736A1
公开(公告)日：2007-02-08
申请号：US11196093
申请日：2005-08-03
申请人： Fabiano Fontana , Steven Fong
发明人： Fabiano Fontana , Steven Fong
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/24
摘要： In one embodiment of the invention, a flash memory is provided that includes: a plurality of flash memory cells sharing a common drain node and a common source node; and a current source that controls the current into the common source node.
摘要翻译：在本发明的一个实施例中，提供一种闪速存储器，其包括：多个共享共同漏极节点和公共源节点的闪存单元; 以及将电流控制到公共源节点的当前源。

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