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1. 发明申请

US20060140944A1 Novel polypeptides involved in immune response 有权
标题翻译：涉及免疫应答的新型多肽
公开(公告)号：US20060140944A1
公开(公告)日：2006-06-29
申请号：US11359254
申请日：2006-02-21
申请人： Steven Yoshinaga , Tak Mak , Arda Shahinian , Anna Bladt , Giorgio Senaldi
发明人： Steven Yoshinaga , Tak Mak , Arda Shahinian , Anna Bladt , Giorgio Senaldi
IPC分类号： A61K39/395 , C12Q1/68 , G01N33/567 , C07H21/04 , C12P21/04 , C07K14/705 , C07K16/28
CPC分类号： C07K14/47 , C07K14/705 , C07K16/2818 , C07K16/2827 , C07K2317/73 , C07K2319/30
摘要： Novel polypeptides which comprise a receptor-ligand pair involved in T-cell activation are disclosed. Nucleic acid molecules encoding said polypeptides, and vectors and host cells for expressing same are also disclosed. The polypeptides, or agonists and antagonists thereof, are used to treat T-cell mediated disorders.
摘要翻译：公开了包含参与T细胞活化的受体 - 配体对的新型多肽。还公开了编码所述多肽的核酸分子，以及用于表达其的载体和宿主细胞。多肽或其激动剂和拮抗剂用于治疗T细胞介导的病症。

2. 发明申请

US20060269565A1 B7 related protein-2 molecules and uses thereof 有权
公开(公告)号：US20060269565A1
公开(公告)日：2006-11-30
申请号：US11229307
申请日：2005-09-16
申请人： Steven Yoshinaga , Woong-Kyung Suh , Tak Mak
发明人： Steven Yoshinaga , Woong-Kyung Suh , Tak Mak
IPC分类号： A61K39/00 , C07H21/04 , C12P21/06 , C07K14/705
CPC分类号： C07K14/70532
摘要： The present invention provides B7 Related Protein-2 (B7RP-2) polypeptides and nucleic acid molecules encoding the same. The invention also provides selective binding agents, vectors, host cells, and methods for producing B7RP-2 polypeptides. The invention further provides pharmaceutical compositions and methods for the diagnosis, treatment, amelioration, and/or prevention of diseases, disorders, and conditions associated with B7RP-2 polypeptides.

3. 发明申请

US20060168489A1 System and shadow circuits with output joining circuit 有权
标题翻译：具有输出接合电路的系统和阴影电路
公开(公告)号：US20060168489A1
公开(公告)日：2006-07-27
申请号：US11044826
申请日：2005-01-26
申请人： Subhasish Mitra , Ming Zhang , Tak Mak , Quan Shi , Kee Kim
发明人： Subhasish Mitra , Ming Zhang , Tak Mak , Quan Shi , Kee Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.
摘要翻译：在一个实施例中，一种装置包括适于在第一输出端产生响应于数据输入信号和至少一个系统时钟信号的第一输出信号的系统电路; 阴影电路，其适于在第二输出端产生响应于所述数据输入信号和所述至少一个系统时钟信号的第二输出信号; 以及耦合到至少第一输出端子和第二输出端子的输出接合电路。

4. 发明申请

US20060168487A1 System pulse latch and shadow pulse latch coupled to output joining circuit 有权
标题翻译：系统脉冲锁存和阴影脉冲锁存器耦合到输出接合电路
公开(公告)号：US20060168487A1
公开(公告)日：2006-07-27
申请号：US11128692
申请日：2005-05-12
申请人： Tak Mak , Ming Zhang , Subhasish Mitra , Paul Shipley
发明人： Tak Mak , Ming Zhang , Subhasish Mitra , Paul Shipley
IPC分类号： G11B20/20 , G06K5/04 , G11B5/00
CPC分类号： H03K3/356156 , G01R31/318583 , H03K3/0375
摘要： In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.
摘要翻译：在一个实施例中，一种装置包括系统脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个系统锁存信号; 阴影脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个阴影锁存信号; 以及耦合到系统脉冲锁存器和阴影脉冲锁存器的输出连接电路，以响应于至少一个系统锁存信号和至少一个阴影锁存信号来提供数据输出信号。

5. 发明申请

US20060005103A1 System and scanout circuits with error resilience circuit 失效
标题翻译：具有错误恢复电路的系统和扫描电路
公开(公告)号：US20060005103A1
公开(公告)日：2006-01-05
申请号：US11050996
申请日：2005-02-04
申请人： Ming Zhang , Subhasish Mitra , Tak Mak , Victor Zia
发明人： Ming Zhang , Subhasish Mitra , Tak Mak , Victor Zia
IPC分类号： G01R31/28 , H03M13/00
CPC分类号： G01R31/318566 , G01R31/31816 , G01R31/318541 , G01R31/318572 , G11C2029/3202
摘要： In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a data input signal and a system clock signal. The scanout circuit is adapted to generate a second output signal in response the data input signal and the system clock signal. The error detecting circuit, coupled to the system circuit and the scanout circuit, is adapted to generate an error signal in response to a relative condition between the first output signal and the second output signal.
摘要翻译：在一个实施例中，设备具有系统电路，扫描输出电路和错误检测电路。系统电路适于响应于数据输入信号和系统时钟信号产生第一输出信号。扫描输出电路适于响应于数据输入信号和系统时钟信号产生第二输出信号。耦合到系统电路和扫描输出电路的误差检测电路适于响应于第一输出信号和第二输出信号之间的相对条件产生误差信号。

6. 发明申请

US20060005091A1 Error detecting circuit 失效
标题翻译：错误检测电路
公开(公告)号：US20060005091A1
公开(公告)日：2006-01-05
申请号：US10882523
申请日：2004-06-30
申请人： Subhasish Mitra , Kee Kim , Tak Mak , Prashant Goteti
发明人： Subhasish Mitra , Kee Kim , Tak Mak , Prashant Goteti
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31816 , G01R31/318566 , G11C2029/3202
摘要： In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
摘要翻译：在一个实施例中，一种装置包括数据路径电路，用于响应于数据输入信号和至少第一数据时钟信号而产生数据输出信号; 阴影电路，耦合到数据路径电路，以在功能操作模式期间响应于数据输入信号和至少第二数据时钟信号产生阴影输出信号，并且响应于扫描信号产生扫描输出信号，在测试操作模式期间的信号和至少第一测试时钟信号; 以及耦合到数据路径和阴影电路的误差检测电路，以响应于数据输出信号和阴影输出信号之间的失配而产生误差信号。

7. 发明申请

US20060052075A1 Testing integrated circuits using high bandwidth wireless technology 审中-公开
标题翻译：使用高带宽无线技术测试集成电路
公开(公告)号：US20060052075A1
公开(公告)日：2006-03-09
申请号：US10936090
申请日：2004-09-07
申请人： Rajeshwar Galivanche , Tak Mak , Sandip Kundu
发明人： Rajeshwar Galivanche , Tak Mak , Sandip Kundu
IPC分类号： H04B1/26
CPC分类号： H01Q1/2283 , G01R31/3025 , H01L2224/16225 , H01L2924/181 , H01L2924/00012
摘要： According to embodiments of the present invention, a UWB (ultra wideband) communication system is employed to wirelessly test and configure circuits on a die. Baseband signals may be utilized with resulting simplification in CMOS circuits, or orthogonal frequency division multiplexing may be employed to allow more than one communication channel. In one embodiment, the antenna for communicating with circuits on a die is placed between the package and the heat spreader, in electrical contact with a solder bump. In another embodiment, the antennas are placed onto wafer scribe lines, and are used to test chips before the wafer is sawed. Other embodiments are described and claimed.
摘要翻译：根据本发明的实施例，采用UWB（超宽带）通信系统对芯片上的电路进行无线测试和配置。可以利用基带信号，从而在CMOS电路中得到简化，或者可以采用正交频分复用来允许多于一个的通信信道。在一个实施例中，用于与管芯上的电路通信的天线放置在封装和散热器之间，与焊料凸块电接触。在另一个实施例中，将天线放置在晶片划线上，并且用于在晶片被锯切之前测试芯片。描述和要求保护其他实施例。

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