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1. 发明授权

US4451900A Method and apparatus for text editing display 失效
标题翻译：用于文本编辑显示的方法和装置
公开(公告)号：US4451900A
公开(公告)日：1984-05-29
申请号：US335471
申请日：1981-12-29
申请人： Steven T. Mayer , Lawrence D. Emmons
发明人： Steven T. Mayer , Lawrence D. Emmons
IPC分类号： G06F17/21 , G06F9/00
CPC分类号： G06F17/212
摘要： In a word processing system that includes a printer for printing text material and a display screen for viewing portions of the display material, a graphical representation of a page of text is displayed for editing purposes, the graphical representation including a plurality of identically formed display elements each corresponding to one of the characters of the text.
摘要翻译：在包括用于打印文本材料的打印机和用于观看显示材料的部分的显示屏幕的文字处理系统中，显示文本页面的图形表示用于编辑目的，图形表示包括多个相同形式的显示元素每个对应于文本的一个字符。

2. 发明授权

US09109295B2 Electrolyte concentration control system for high rate electroplating 有权
标题翻译：高速电镀电解质浓度控制系统
公开(公告)号：US09109295B2
公开(公告)日：2015-08-18
申请号：US12577619
申请日：2009-10-12
申请人： Jonathan D. Reid , Seshasayee Varadarajan , Steven T. Mayer
发明人： Jonathan D. Reid , Seshasayee Varadarajan , Steven T. Mayer
IPC分类号： C25D17/00 , C25D21/18 , C25D3/38 , C25D21/02 , C25D21/14 , C25D7/12
CPC分类号： C25D17/00 , C25D3/38 , C25D7/123 , C25D17/001 , C25D21/02 , C25D21/14 , C25D21/18
摘要： An electroplating apparatus for filling recessed features on a semiconductor substrate includes an electrolyte concentrator configured for concentrating an electrolyte having Cu2+ ions to form a concentrated electrolyte solution that would have been supersaturated at 20° C. The electrolyte is maintained at a temperature that is higher than 20° C., such as at least at about 40° C. The apparatus further includes a concentrated electrolyte reservoir and a plating cell, where the plating cell is configured for electroplating with concentrated electrolyte at a temperature of at least about 40° C. Electroplating with electrolytes having Cu2+ concentration of at least about 60 g/L at temperatures of at least about 40° C. results in very fast copper deposition rates, and is particularly well-suited for filling large, high aspect ratio features, such as through-silicon vias.
摘要翻译：用于在半导体衬底上填充凹陷特征的电镀设备包括电解质浓缩器，其被配置用于浓缩具有Cu 2+离子的电解质，以形成在20℃下已经过饱和的浓缩电解质溶液。电解质保持在高于 20℃，例如至少约40℃。该设备还包括浓缩电解质储存器和电镀池，其中电镀单元被配置为在至少约40℃的温度下用浓缩电解质电镀。在至少约40℃的温度下，具有Cu2 +浓度至少约60g / L的电解质的电镀导致非常快的铜沉积速率，并且特别适合于填充大的高纵横比特征，例如通过硅通孔。

3. 发明授权

US08513124B1 Copper electroplating process for uniform across wafer deposition and void free filling on semi-noble metal coated wafers 有权
标题翻译：铜电镀工艺，用于跨晶片沉积均匀并在半贵金属涂覆的晶片上无空隙填充
公开(公告)号：US08513124B1
公开(公告)日：2013-08-20
申请号：US12785205
申请日：2010-05-21
申请人： Thomas A. Ponnuswamy , John H. Sukamto , Jonathan D. Reid , Steven T. Mayer
发明人： Thomas A. Ponnuswamy , John H. Sukamto , Jonathan D. Reid , Steven T. Mayer
IPC分类号： H01L21/44
CPC分类号： H01L21/76873 , C25D3/38 , C25D5/18 , C25D5/50 , C25D7/123 , H01L21/2885 , H01L21/76843 , H01L21/76864 , H01L2221/1089
摘要： Disclosed are methods of depositing a copper seed layer to be used for subsequent electroplating a bulk-layer of copper thereon. A copper seed layer may be deposited with different processes, including CVD, PVD, and electroplating. With electroplating methods for depositing a copper seed layer, disclosed are methods for depositing a copper alloy seed layer, methods for depositing a copper seed layer on the semi-noble metal layer with a non-corrosive electrolyte, methods of treating the semi-noble metal layer that the copper seed layer is deposited on, and methods for promoting a more uniform copper seed layer deposition across a semiconductor wafer.
摘要翻译：公开了一种沉积铜籽晶层的方法，该铜籽晶层用于随后电镀铜的体层。铜种子层可以以不同的工艺沉积，包括CVD，PVD和电镀。利用用于沉积铜籽晶层的电镀方法，公开了用于沉积铜合金晶种层的方法，用非腐蚀性电解质在半贵金属层上沉积铜籽晶层的方法，处理半贵金属的方法沉积铜籽晶层的层，以及用于促进越过半导体晶片的更均匀的铜籽晶层沉积的方法。

4. 发明授权

US08500985B2 Photoresist-free metal deposition 有权
公开(公告)号：US08500985B2
公开(公告)日：2013-08-06
申请号：US11827800
申请日：2007-07-13
申请人： Steven T. Mayer , John Stephen Drewery , Eric G. Webb
发明人： Steven T. Mayer , John Stephen Drewery , Eric G. Webb
IPC分类号： C25D5/34 , C25D5/00 , C25D5/02 , B05D5/00
CPC分类号： C25D5/022 , C25F5/00 , H05K3/07 , H05K3/108 , H05K2203/0108 , H05K2203/0392 , H05K2203/0537 , H05K2203/0713
摘要： Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.

5. 发明授权

US08481432B2 Fabrication of semiconductor interconnect structure 有权
公开(公告)号：US08481432B2
公开(公告)日：2013-07-09
申请号：US13116963
申请日：2011-05-26
申请人： Steven T. Mayer , Daniel A. Koos , Eric Webb
发明人： Steven T. Mayer , Daniel A. Koos , Eric Webb
IPC分类号： H01L21/302
CPC分类号： C23F1/02 , C23C18/1608 , C23C18/1834 , C23F1/18 , C23F1/34 , H01L21/288 , H01L21/32134 , H01L21/76849 , H01L21/76856 , H01L21/76858 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions.

6. 发明授权

US08475637B2 Electroplating apparatus with vented electrolyte manifold 有权
标题翻译：带排气电解液歧管的电镀设备
公开(公告)号：US08475637B2
公开(公告)日：2013-07-02
申请号：US12337147
申请日：2008-12-17
申请人： Jingbin Feng , Zhian He , Robert Rash , Steven T. Mayer
发明人： Jingbin Feng , Zhian He , Robert Rash , Steven T. Mayer
IPC分类号： C25D17/00 , C25D21/04
CPC分类号： C25D7/123 , C25D17/001 , C25D17/002
摘要： Embodiments related to increasing a uniformity of an electroplated film are disclosed. For example, one disclosed embodiment provides an electroplating apparatus comprising a plating chamber, a work piece holder, a cathode contact configured to electrically contact a work piece, and an anode contact configured to electrically contact an anode disposed in the plating chamber. A diffusing barrier is disposed between the cathode contact and the anode contact to provide a uniform electrolyte flow to the work piece, and electrolyte delivery and return paths are provided for delivering electrolyte to and away from the plating chamber. Additionally, a vented electrolyte manifold is disposed in the electrolyte delivery path immediately upstream of the plating chamber, the vented electrolyte manifold comprising one or more electrolyte delivery openings that open to the plating chamber and one or more vents that open to a location other than the plating chamber.
摘要翻译：公开了与提高电镀膜的均匀性有关的实施例。例如，一个公开的实施例提供了一种电镀设备，其包括电镀室，工件保持器，构造成电接触工件的阴极接触件和被配置为电接触设置在电镀室中的阳极的阳极接触件。扩散阻挡层设置在阴极接触件和阳极接触件之间，以提供均匀的电解质流向工件，并且提供电解质输送和返回路径用于将电解质输送到电镀室和远离电镀室。另外，排气的电解液歧管设置在紧邻镀室的上游的电解质输送路径中，排出的电解质歧管包括一个或多个向电镀室敞开的电解质输送开口，以及一个或多个通向出口电镀室。

7. 发明授权

US08419964B2 Apparatus and method for edge bevel removal of copper from silicon wafers 有权
标题翻译：用于从硅晶片去除铜的边缘斜面的设备和方法
公开(公告)号：US08419964B2
公开(公告)日：2013-04-16
申请号：US12199412
申请日：2008-08-27
申请人： Kousik Ganesan , Shanthinath Ghongadi , Tariq Majid , Aaron Labrie , Steven T. Mayer
发明人： Kousik Ganesan , Shanthinath Ghongadi , Tariq Majid , Aaron Labrie , Steven T. Mayer
IPC分类号： H01L21/302
CPC分类号： H01L21/6708 , H01L21/02068 , H01L21/02087 , H01L21/0209 , H01L21/32134 , H01L21/67745 , H01L21/68735 , H01L21/68785
摘要： Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.
摘要翻译：描述了用于从半导体晶片的边缘斜面区域去除金属的化学蚀刻方法和相关模块。在晶片的边缘斜面区域上施加蚀刻剂之前，该方法和系统提供了薄层的预漂洗液体。蚀刻剂较少稀释，并通过稀薄的冲洗液层更快地扩散。公开了一种边缘斜面去除实施例，其涉及在减少加工时间，使金属锥度变窄并允许随后的化学机械抛光方面特别有效。

8. 发明申请

US20110284386A1 THROUGH SILICON VIA FILLING USING AN ELECTROLYTE WITH A DUAL STATE INHIBITOR 有权
标题翻译：通过使用电解液与双态抑制剂进行填充的硅
公开(公告)号：US20110284386A1
公开(公告)日：2011-11-24
申请号：US13110488
申请日：2011-05-18
申请人： Mark J. Willey , Steven T. Mayer
发明人： Mark J. Willey , Steven T. Mayer
IPC分类号： C25D5/02 , C25D19/00 , C25D3/38
CPC分类号： C25D3/38 , C25D5/022 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76879 , H01L21/76898 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A method for electrofilling large, high aspect ratio recessed features with copper without depositing substantial amounts of copper in the field region is provided. The method allows completely filling recessed features having aspect ratios of at least about 5:1 such as at least about 10:1, and widths of at least about 1 μm in a substantially void-free manner without depositing more than 5% of copper in the field region (relative to the thickness deposited in the recessed feature). The method involves contacting the substrate having one or more large, high aspect ratio recessed features (such as a TSVs) with an electrolyte comprising copper ions and an organic dual state inhibitor (DSI) configured for inhibiting copper deposition in the field region, and electrodepositing copper under potential-controlled conditions, where the potential is controlled not exceed the critical potential of the DSI.
摘要翻译：提供了一种用于电镀大量，高纵横比的凹陷特征与铜而不在现场区域中沉积大量铜的方法。该方法允许以基本无空隙的方式完全填充具有至少约5:1的纵横比（例如至少约10:1）和至少约1μm的宽度的凹陷特征，而不沉积超过5％的铜场区域（相对于沉积在凹陷特征中的厚度）。该方法包括将具有一个或多个大的，高纵横比的凹陷特征（例如TSV）的基底与包含铜离子的电解质和被配置用于抑制场区中的铜沉积的有机双态抑制剂（DSI）接触，以及电沉积在电势控制条件下，电位控制的铜不超过DSI的临界电位。

9. 发明授权

US08026174B1 Sequential station tool for wet processing of semiconductor wafers 有权
标题翻译：用于半导体晶圆湿法处理的顺序工具
公开(公告)号：US08026174B1
公开(公告)日：2011-09-27
申请号：US12496120
申请日：2009-07-01
申请人： Evan E. Patton , Theodore Cacouris , Eliot Broadbent , Steven T. Mayer
发明人： Evan E. Patton , Theodore Cacouris , Eliot Broadbent , Steven T. Mayer
IPC分类号： H01L21/445 , C25D17/28
CPC分类号： C25D17/001 , C25D3/38 , C25D5/10 , H01L21/2885 , H01L21/67161 , H01L21/6719 , H01L21/6723 , H01L21/67751 , H01L21/76877 , Y10T29/41
摘要： Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.
摘要翻译：提供了顺序处理半导体晶片的方法和装置。顺序过程采用多工位处理模块，其中特别包含的晶片工艺被分为子工艺，每个子工艺被优化用于增加晶圆到晶片的均匀性，结果质量和整个晶片生产量。在一个示例中，铜电镀模块包括用于润湿，起始，种子层修复，填充，覆盖层，回收和冲洗的分离站。

10. 发明申请

US20090277801A1 Photoresist-free metal deposition 有权
标题翻译：无光致抗蚀剂金属沉积
公开(公告)号：US20090277801A1
公开(公告)日：2009-11-12
申请号：US11890541
申请日：2007-08-06
申请人： Steven T. Mayer , John Stephen Drewery , Eric G. Webb
发明人： Steven T. Mayer , John Stephen Drewery , Eric G. Webb
IPC分类号： B23H3/00 , B05D3/00 , C25B9/00
CPC分类号： C25D5/022 , C25F5/00 , H05K3/07 , H05K3/108 , H05K2203/0108 , H05K2203/0392 , H05K2203/0537 , H05K2203/0713
摘要： Selectively accelerated or selectively inhibited metal deposition is performed to form metal structures of an electronic device. A desired pattern of an accelerator or of an inhibitor is applied to the substrate; for example, by stamping the substrate with a patterned stamp or spraying a solution using an inkjet printer. In other embodiments, a global layer of accelerator or inhibitor is applied to a substrate and selectively modified in a desired pattern. Thereafter, selective metal deposition is performed.
摘要翻译：进行选择性加速或选择性抑制金属沉积以形成电子器件的金属结构。将所需的促进剂或抑制剂的图案施加到基材上; 例如，通过用图案化的印模冲压基板或使用喷墨打印机喷涂溶液。在其它实施方案中，将全局加速剂或抑制剂层施加到基底上并以期望的图案选择性地修饰。此后，进行选择性金属沉积。

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