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1. 发明授权

US5920202A Configurable logic element with ability to evaluate five and six input functions 失效
标题翻译：可配置逻辑元件，具有评估五个和六个输入功能的能力
公开(公告)号：US5920202A
公开(公告)日：1999-07-06
申请号：US835088
申请日：1997-04-04
申请人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177 , G06F7/38
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17704
摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a first six-input-function multiplexer or function generator, and with a different sixth independent input in a second six-input-function multiplexer or function generator. The two six-input-function multiplexers or function generators therefore produce two outputs of which one can be any function of six inputs; the other output can be any function of six inputs provided that five inputs are shared between the two 6-input functions. Some functions of up to nineteen inputs can also be generated in a single CLE.
摘要翻译：本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。根据本发明的CLE具有四个功能发生器。两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入组合，以产生可以是五个输入或多达九个输入的一些功能的输出。其他两个功能发生器的输出类似地组合。然后，两个五输入功能多路复用器或函数发生器的输出与第六个六输入函数多路复用器或函数发生器中的第六个独立输入组合，并在第六个六输入函数中与不同的第六独立输入进行组合多路复用器或函数发生器。因此，两个六输入功能多路复用器或函数发生器产生两个输出，其中一个可以是六个输入的任何功能; 另外的输出可以是六个输入的任何功能，只要在两个6输入功能之间共享五个输入。也可以在单个CLE中生成多达十九个输入的某些功能。

2. 发明授权

US5914616A FPGA repeatable interconnect structure with hierarchical interconnect lines 失效
标题翻译：具有分层互连线路的FPGA可重复互连结构
公开(公告)号：US5914616A
公开(公告)日：1999-06-22
申请号：US806997
申请日：1997-02-26
申请人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
发明人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17796 , H03K19/1737 , H03K19/17704
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.
摘要翻译：本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径和瓷砖有一段距离。可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片，然后继续并连接到瓦片六瓦片。在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。

3. 发明授权

US06448808B2 Interconnect structure for a programmable logic device 有权
公开(公告)号：US06448808B2
公开(公告)日：2002-09-10
申请号：US09929977
申请日：2001-08-15
申请人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
发明人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
IPC分类号： H01L2500
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

4. 发明授权

US6107827A FPGA CLE with two independent carry chains 有权
标题翻译： FPGA CLE具有两个独立的进位链
公开(公告)号：US6107827A
公开(公告)日：2000-08-22
申请号：US311782
申请日：1999-05-13
申请人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
发明人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： The invention provides an FPGA comprising an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE). In one embodiment, the CLE is implemented in two similar portions called "slices". Each slice has a separate carry chain. In a CLE with four function generators, each carry chain incorporates the outputs of two function generators.
摘要翻译：本发明提供了一种包括相同瓦片阵列的FPGA。每个瓦片包括包括可配置逻辑元件（CLE）的逻辑块。在一个实施例中，CLE以称为“切片”的两个相似部分实现。每个切片都有一个单独的进位链。在具有四个功能发生器的CLE中，每个进位链包含两个功能发生器的输出。

5. 发明授权

US06362648B1 Multiplexer for implementing logic functions in a programmable logic device 有权
标题翻译：用于在可编程逻辑器件中实现逻辑功能的多路复用器
公开(公告)号：US06362648B1
公开(公告)日：2002-03-26
申请号：US09712038
申请日：2000-11-13
申请人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Bernard J. New , Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/1778
摘要： The invention allows the implementation of common wide logic functions using only two function generators of a field programmable gate array. One embodiment of the invention provides a structure for implementing a wide AND-gate in an FPGA configurable logic element (CLE) or portion thereof that includes no more than two function generators. First and second function generators are configured as AND-gates, the output signals (first and second AND signals) being combined in a 2-to-1 multiplexer controlled by the first AND signal, “0” selecting the first AND signal and “1” selecting the second AND signal. Therefore, a wide AND-gate is provided having a number of input signals equal to the total number of input signals for the two function generators. In another embodiment, a wide OR-gate is provided by configuring the function generators as OR-gates and controlling the multiplexer using the second OR signal.
摘要翻译：本发明允许仅使用现场可编程门阵列的两个函数发生器实现普通的宽逻辑功能。本发明的一个实施例提供了一种用于在FPGA可配置逻辑元件（CLE）或其部分中实现宽的与门的结构，其包括不超过两个功能发生器。第一和第二功能发生器被配置为与门，输出信号（第一和第二AND信号）被组合在由第一AND信号控制的2对1多路复用器中，选择第一AND信号为“0”和“1” “选择第二个AND信号。因此，提供了具有等于两个功能发生器的输入信号的总数的多个输入信号的宽AND门。在另一个实施例中，通过将功能发生器配置为OR门并使用第二OR信号来控制多路复用器来提供宽的或门。

6. 发明授权

US06292022B1 Interconnect structure for a programmable logic device 有权
公开(公告)号：US06292022B1
公开(公告)日：2001-09-18
申请号：US09759051
申请日：2001-01-11
申请人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
发明人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
IPC分类号： H01L2500
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.

7. 发明授权

US6124731A Configurable logic element with ability to evaluate wide logic functions 有权
标题翻译：可配置逻辑元件，具有评估宽逻辑功能的能力
公开(公告)号：US6124731A
公开(公告)日：2000-09-26
申请号：US480845
申请日：2000-01-10
申请人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
发明人： Steven P. Young , Shekhar Bapat , Kamal Chaudhary , Trevor J. Bauer , Roman Iwanczuk
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737 , H03K19/17704
摘要： The invention provides a Configurable Logic Element (CLE) preferably included in each of an array of identical tiles. A CLE according to the invention has four function generators. The outputs of two function generators are combined with a fifth independent input in a five-input-function multiplexer or function generator to produce an output that can be any function of five inputs, or some functions of up to nine inputs. The outputs of the other two function generators are similarly combined. The outputs of the two five-input-function multiplexers or function generators are then combined with a sixth independent input in a six-input-function multiplexer or function generator. The six-input-function multiplexer or function generator therefore produces an output that can be any function of up to six inputs. Some functions of up to nineteen inputs can also be generated in a single CLE.
摘要翻译：本发明提供了优选地包括在相同瓦片的阵列中的每一个中的可配置逻辑元件（CLE）。根据本发明的CLE具有四个功能发生器。两个功能发生器的输出与五输入功能多路复用器或函数发生器中的第五个独立输入相结合，以产生可以是五个输入或多达九个输入的一些功能的输出。其他两个功能发生器的输出类似地组合。然后，两个五输入功能多路复用器或函数发生器的输出与六输入函数多路复用器或函数发生器中的第六个独立输入相组合。因此，六输入功能多路复用器或函数发生器产生的输出可以是多达六个输入的任何功能。也可以在单个CLE中生成多达十九个输入的某些功能。

8. 发明授权

US5963050A Configurable logic element with fast feedback paths 失效
标题翻译：具有快速反馈路径的可组态逻辑元件
公开(公告)号：US5963050A
公开(公告)日：1999-10-05
申请号：US823265
申请日：1997-03-24
申请人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
发明人： Steven P. Young , Bernard J. New , Nicolas John Camilleri , Trevor J. Bauer , Shekhar Bapat , Kamal Chaudhary , Sridhar Krishnamurthy
IPC分类号： H01L25/00 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.
摘要翻译：本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。每个瓦片包括包括可配置逻辑元件（CLE）和输出多路复用器的逻辑块。在逻辑块内提供快速反馈路径，以将CLE输出直接或通过输入多路复用器连接到CLE输入。快速反馈路径绕过输出多路复用器，因此提供比在大多数常规FPGA逻辑块中可以获得的更快的反馈。在一个实施例中，快速反馈路径提供了一个CLE中的所有功能发生器通过快速反馈路径彼此驱动的能力，而不管逻辑如何映射到CLE的函数发生器中。

9. 发明授权

US5942913A FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines 失效
标题翻译： FPGA具有双向和单向互连线的可重复互连结构
公开(公告)号：US5942913A
公开(公告)日：1999-08-24
申请号：US821263
申请日：1997-03-20
申请人： Steven P. Young , Trevor J. Bauer , Kamal Chaudhary , Sridhar Krishnamurthy
发明人： Steven P. Young , Trevor J. Bauer , Kamal Chaudhary , Sridhar Krishnamurthy
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/1778
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. The interconnect structure includes both buffered and unbuffered interconnect lines. Some buffered interconnect lines are bidirectional, and others are unidirectional. A carefully selected mixture of unidirectional and bidirectional lines provides a balance of flexibility, silicon area, and performance.
摘要翻译：本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。互连结构包括缓冲和非缓冲互连线。一些缓冲的互连线是双向的，而另一些是单向的。精心挑选的单向和双向线路混合物提供了灵活性，硅面积和性能的平衡。

10. 发明授权

US06204690B1 FPGA architecture with offset interconnect lines 有权
标题翻译：具有偏移互连线路的FPGA架构
公开(公告)号：US06204690B1
公开(公告)日：2001-03-20
申请号：US09574741
申请日：2000-05-18
申请人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
发明人： Steven P. Young , Kamal Chaudhary , Trevor J. Bauer
IPC分类号： H01L2500
CPC分类号： H03K19/1737 , H03K19/17704 , H03K19/17736 , H03K19/17796
摘要： The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.
摘要翻译：本发明提供了优选地包括在相同瓦片阵列中的FPGA互连结构。连接到相邻瓦片的单条线和连接到瓦片几个瓦片的中间线的组合创建互连层级，其允许任何逻辑块连接到任何其他逻辑块，但是也允许到相邻瓦片的快速路径和瓷砖有一段距离。可以将更长的互连线包括为第三层次以允许广泛分隔的瓷砖的互连。在优选实施例中，从给定的瓦片中，中间线连接到瓦片三瓦片之外，然后继续并连接到瓦片六瓦片。在该实施例中，中间长度线不连接到中间瓦片一个，两个，四个和五个瓦片。

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