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1. 发明授权

US06735543B2 Method and apparatus for testing, characterizing and tuning a chip interface 失效
标题翻译：用于测试，表征和调整芯片接口的方法和装置
公开(公告)号：US06735543B2
公开(公告)日：2004-05-11
申请号：US09996839
申请日：2001-11-29
申请人： Steven Michael Douskey , Daniel Mark Dreps , Frank David Ferraiolo , Curtis Walter Preuss , Robert James Reese , Paul William Rudrud , James Donald Ryan , Robert Russell Williams
发明人： Steven Michael Douskey , Daniel Mark Dreps , Frank David Ferraiolo , Curtis Walter Preuss , Robert James Reese , Paul William Rudrud , James Donald Ryan , Robert Russell Williams
IPC分类号： G06F1900
CPC分类号： G01R31/31813 , G01R31/318385
摘要： An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.
摘要翻译：传输芯片中的芯片间线路传输电路和接收芯片中的互补接收电路通过在两个芯片上分别产生相同的伪随机测试数据，比较数据和记录错误，提供表征芯片间接口的能力。优选地，可以在单独的线路基础上调整一个或两个芯片以通过改变阈值检测电压，信号延迟和/或驱动器功率来减少误差。接收机电路优选地包含用于对测试周期和错误进行计数的计数器，其可以针对任何特定线路或类型的错误被屏蔽。因此，根据优选实施例的可调谐和可表征的接口因此支持针对各种调谐参数设置在各个线路上准确地确定低错误率。

2. 发明授权

US5949249A Driver having inductance-controlled current slew rate 失效
标题翻译：驱动器具有电感控制电流转换速率
公开(公告)号：US5949249A
公开(公告)日：1999-09-07
申请号：US838572
申请日：1997-04-10
申请人： Curtis Walter Preuss , Robert Russell Williams
发明人： Curtis Walter Preuss , Robert Russell Williams
IPC分类号： H03K17/16
CPC分类号： H03K17/166
摘要： A control system for minimizing and controlling the current slew rate of an output device by using inductance to directly measure the current slew rate is provided. The control system may, for example, be used to control and minimize the current slew rate through signal drivers and allow for faster drivers and/or larger numbers of drivers on integrated circuit chips. In accordance with one embodiment of the invention, an inductor is serially coupled with an output device. A predriver is coupled to the gate of the output device for providing a voltage slew rate at the output device gate. A comparator is coupled to the inductor for sensing a voltage indicative of a current slew rate through the inductor and outputing a signal indicating whether the current slew rate exceeds or falls below a desired level. A controller responsive to the comparator is provided for controlling the driver to increase and decrease the voltage slew rate at the output device gate when the comparator signal indicates that the current slew rate respectively falls below and exceeds the desired level, thereby controlling the current slew rate through the inductor and through the output device.
摘要翻译：提供一种用于通过使用电感来最小化和控制输出装置的电流转换速率以直接测量当前转换速率的控制系统。例如，控制系统可以用于通过信号驱动器来控制和最小化电流转换速率，并且允许集成电路芯片上的更快的驱动器和/或更大数量的驱动器。根据本发明的一个实施例，电感器与输出装置串联耦合。预驱动器耦合到输出装置的栅极，以在输出装置门处提供电压转换速率。比较器耦合到电感器，用于感测指示通过电感器的电流转换速率的电压，并输出指示电流转换速率是否超过或低于期望电平的信号。提供响应于比较器的控制器，用于当比较器信号指示电流转换速率分别低于并超过期望电平时控制驱动器增加和降低输出器件栅极处的电压转换速率，由此控制电流转换速率通过电感和通过输出装置。

3. 发明授权

US06600347B2 Dynamically producing an effective impedance of an output driver with a bounded variation during transitions thereby reducing jitter 失效
标题翻译：在转换期间动态地产生具有有界变化的输出驱动器的有效阻抗，从而减少抖动
公开(公告)号：US06600347B2
公开(公告)日：2003-07-29
申请号：US09974686
申请日：2001-10-10
申请人： John Michael Borkenhagen , Moises Cases , Daniel Mark Dreps , David LeRoy Guertin , Nam Huu Pham , Robert Russell Williams
发明人： John Michael Borkenhagen , Moises Cases , Daniel Mark Dreps , David LeRoy Guertin , Nam Huu Pham , Robert Russell Williams
IPC分类号： H03B100
CPC分类号： H03K17/164
摘要： A method and system for reducing a reflection coefficient below a predetermined value thereby reducing jitter by the variation of the effective impedance of a driver appearing to be bounded during state transitions. The driver may include a pull-up driver and a pull-down driver. In the pull-up driver, the transistors may be switched from a first state to a second state in a staggered fashion where the first state is complementary to the second state; In the pull-down driver, the transistors may be switched from a second state to a first state in a staggered fashion. By staggering the switching of the transistors in the pull-up driver and the pull-down driver, a portion of the current may flow from the pull-up driver to the pull-down driver thereby causing the variation of the effective impedance of the driver to appear to be bounded during state transitions.
摘要翻译：一种用于将反射系数降低到低于预定值的方法和系统，从而通过在状态转换期间看起来被界定的驱动器的有效阻抗的变化来减少抖动。驱动器可以包括上拉驱动器和下拉驱动器。在上拉驱动器中，晶体管可以以第一状态与第二状态互补的交错方式从第一状态切换到第二状态; 在下拉驱动器中，晶体管可以以交错的方式从第二状态切换到第一状态。通过交错上拉驱动器和下拉驱动器中的晶体管的切换，电流的一部分可以从上拉驱动器流向下拉驱动器，从而导致驱动器的有效阻抗的变化在状态转换期间看起来是有界的。

4. 发明授权

US06229372B1 Active clamp network for multiple voltages 失效
标题翻译：多电压有源钳位网络
公开(公告)号：US06229372B1
公开(公告)日：2001-05-08
申请号：US09443609
申请日：1999-11-19
申请人： Benjamin William Mashak , Robert Russell Williams , Steven Howard Voldman , David TinSun Hui
发明人： Benjamin William Mashak , Robert Russell Williams , Steven Howard Voldman , David TinSun Hui
IPC分类号： H03K508
CPC分类号： H03K5/08
摘要： An active clamp circuit for digital circuits includes a first MOSFET serially connected between an upper power supply voltage and an input terminal to be clamped, and a second MOSFET serially connected between a lower voltage power supply and the input terminal. The voltages at the gates of the first and second MOSFETs are held at constant first and second reference voltages by a reference circuit and the first reference voltage at the gate of the first MOSFET is less than the second reference voltage at the gate of the second MOSFET. The first and second reference voltages can be changed by connecting the reference circuit to power supply voltages other than the power supply voltages to which the first and second MOSFETs are connected. The reference voltages can also be varied by adding stages of transistors which act as resistors in parallel to the reference circuit. When the first reference voltage is to be varied, it is recommended that the transistors of opposite type be biased independently. The clamping action can be switched on or off, and when the clamping action is switched off, the voltage on the first and second MOSFETs is kept from floating by connecting the gates to turn-off transistors. The device is particularly suited for use with silicon-on-insulator.
摘要翻译：用于数字电路的有源钳位电路包括串联连接在上电源电压和要钳位的输入端之间的第一MOSFET和串联连接在低压电源与输入端之间的第二MOSFET。第一和第二MOSFET的栅极处的电压通过参考电路保持在恒定的第一和第二参考电压，并且第一MOSFET的栅极处的第一参考电压小于第二MOSFET的栅极处的第二参考电压。可以通过将参考电路连接到除了连接有第一和第二MOSFET的电源电压之外的电源电压来改变第一和第二参考电压。参考电压也可以通过添加用作与参考电路并联的电阻器的晶体管级来改变。当要改变第一个参考电压时，建议相反类型的晶体管被独立地偏置。可以打开或关闭夹紧动作，并且当夹紧动作关闭时，通过将栅极连接到截止晶体管，第一和第二MOSFET上的电压不会浮起。该器件特别适用于绝缘体上硅。

5. 发明授权

US6111422A Method of testing susceptibility to failure of functional circuitry embodied in an integrated circuit 失效
标题翻译：对集成电路中实现的功能电路的故障敏感性测试方法
公开(公告)号：US6111422A
公开(公告)日：2000-08-29
申请号：US303793
申请日：1999-04-30
申请人： Salvatore Nickolas Storino , Robert Russell Williams
发明人： Salvatore Nickolas Storino , Robert Russell Williams
IPC分类号： G01R31/30 , G01R31/02
CPC分类号： G01R31/30
摘要： A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.
摘要翻译：在芯片上形成测试装置，其允许在要测试的芯片上形成的功能电路的故障敏感性。测试设备允许通过测试在芯片制造过程中引入的设计规范的偏差是否足以导致功能电路故障，包括敏感电路（例如预充电动态逻辑）的芯片的积极设计。

6. 发明授权

US06049218A Semiconductor device having embedded test device for testing design specifications 失效
标题翻译：具有用于测试设计规格的嵌入式测试装置的半导体器件
公开(公告)号：US06049218A
公开(公告)日：2000-04-11
申请号：US062134
申请日：1998-04-17
申请人： Salvatore Nickolas Storino , Robert Russell Williams
发明人： Salvatore Nickolas Storino , Robert Russell Williams
IPC分类号： G01R31/30 , G01R31/28
CPC分类号： G01R31/30
摘要： A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.
摘要翻译：在芯片上形成测试装置，其允许在要测试的芯片上形成的功能电路的故障敏感性。测试设备允许通过测试在芯片制造过程中引入的设计规范的偏差是否足以导致功能电路故障，包括敏感电路（例如预充电动态逻辑）的芯片的积极设计。

7. 发明授权

US6150869A Method and apparatus for body control in silicon-on-insulator (SOI) domino circuits 失效
标题翻译：绝缘体上硅（SOI）多米诺骨牌电路中的身体控制方法和装置
公开(公告)号：US6150869A
公开(公告)日：2000-11-21
申请号：US289034
申请日：1999-04-09
申请人： Salvatore N. Storino , Jeff V. Tran , Robert Russell Williams
发明人： Salvatore N. Storino , Jeff V. Tran , Robert Russell Williams
IPC分类号： H03K19/096 , H03K3/01
CPC分类号： H03K19/0963
摘要： Methods and apparatus are provided for body control in silicon-on-insulator (SOI) domino circuits. The silicon-on-insulator (SOI) domino circuit includes a clock input and an input transistor stack including a plurality of input transistors. Each of the plurality of input transistors receives a data input. An intermediate precharge node is connected to the input transistor stack. An output inverter is connected to the intermediate precharge node. The output inverter includes a pair of silicon-on-insulator (SOI) transistors. A clocked transistor is connected to a body of at least one of the pair of silicon-on-insulator (SOI) transistors. The clocked transistor predischarges the body of the SOI transistor. Another clocked transistor is connected between ground and a body of an evaluate transistor connected to the input transistor stack. The body of the evaluate transistor is predischarged by the clocked transistor.
摘要翻译：提供了用于绝缘体上硅（SOI）多米诺骨牌电路中的身体控制的方法和装置。绝缘体上硅（SOI）多米诺骨电路包括时钟输入和包括多个输入晶体管的输入晶体管堆叠。多个输入晶体管中的每一个接收数据输入。中间预充电节点连接到输入晶体管堆叠。输出反相器连接到中间预充电节点。输出反相器包括一对绝缘体上硅（SOI）晶体管。时钟晶体管连接到一对绝缘体上硅（SOI）晶体管中的至少一个的主体。时钟晶体管会牺牲SOI晶体管的体积。另一个时钟晶体管连接在接地和连接到输入晶体管堆叠的评估晶体管的主体之间。评估晶体管的主体由时钟晶体管预充电。

8. 发明授权

US6094072A Methods and apparatus for bipolar elimination in silicon-on-insulator (SOI) domino circuits 有权
标题翻译：绝缘体上硅（SOI）多米诺骨电路中双极消除的方法和装置
公开(公告)号：US6094072A
公开(公告)日：2000-07-25
申请号：US268923
申请日：1999-03-16
申请人： Andrew Douglas Davies , Salvatore N. Storino , Jeff V. Tran , Robert Russell Williams
发明人： Andrew Douglas Davies , Salvatore N. Storino , Jeff V. Tran , Robert Russell Williams
IPC分类号： H01L27/08 , H01L21/8238 , H01L27/092 , H01L29/786 , H03K19/003 , H03K19/094 , H03K19/096 , H03K19/20
CPC分类号： H03K19/00315 , H01L27/0921 , H03K19/094
摘要： In brief, methods and apparatus are provided for bipolar elimination in silicon-on-insulator (SOI) domino circuits. Apparatus for bipolar elimination in silcon-on-insulator (SOI) domino circuit includes a domino silicon-on-insulator (SOI) field effect transistor. An input is coupled to the domino silicon-n-insulator (SOI) field effect transistor. A predischarging device is coupled to said domino silicon-on-insulator (SOI) field effect transistor. The predischarging device is activated during a precharge mode of the domino circuit, so that the SOI parasitic bipolar transistor is not activated. A dynamic input circuit couples the input to the domino silicon-on-insulator (SOI) field effect transistor. The output of the dynamic input circuit is low during the precharge mode. The output of the dynamic input circuit corresponds to the input during the evaluate mode. The output of the dynamic input circuit is used to gate the predischarging device.
摘要翻译：简而言之，提供了用于绝缘体上硅（SOI）多米诺骨电路中的双极消除的方法和装置。在绝缘体上硅（SOI）多米诺骨电路中双极消除的装置包括绝缘体上硅（SOI）场效应晶体管。输入耦合到多米诺硅绝缘体（SOI）场效应晶体管。预充电器件耦合到所述多硅绝缘体（SOI）场效应晶体管。预充电器件在多米诺骨电路的预充电模式下被激活，使得SOI寄生双极晶体管不被激活。动态输入电路将输入耦合到绝缘体上硅（SOI）场效应晶体管。在预充电模式期间，动态输入电路的输出为低电平。动态输入电路的输出对应于评估模式下的输入。动态输入电路的输出用于对预充电设备进行门控。

9. 发明授权

US6005406A Test device and method facilitating aggressive circuit design 失效
标题翻译：有利于电路设计的测试装置和方法
公开(公告)号：US6005406A
公开(公告)日：1999-12-21
申请号：US568743
申请日：1995-12-07
申请人： Salvatore Nickolas Storino , Robert Russell Williams
发明人： Salvatore Nickolas Storino , Robert Russell Williams
IPC分类号： G01R31/30 , G01R31/22
CPC分类号： G01R31/30
摘要： A test device is formed on a chip which allows the susceptibility to failure of functional circuitry formed on the chip to be tested. The test device allows aggressive design of chips which include sensitive circuitry, such as precharged dynamic logic, by testing whether deviations from the design specification introduced during manufacturing of the chip are sufficient to cause failure of the functional circuitry.
摘要翻译：在芯片上形成测试装置，其允许在要测试的芯片上形成的功能电路的故障敏感性。测试设备允许通过测试在芯片制造过程中引入的设计规范的偏差是否足以导致功能电路故障，包括敏感电路（例如预充电动态逻辑）的芯片的积极设计。

10. 发明授权

US06940955B1 Method and remote answering machine controller for programmable control based upon message importance 失效
标题翻译：基于消息重要性的方法和远程应答机控制器进行可编程控制
公开(公告)号：US06940955B1
公开(公告)日：2005-09-06
申请号：US09547597
申请日：2000-04-11
申请人： Steven Paul Jones , Robert Russell Williams
发明人： Steven Paul Jones , Robert Russell Williams
IPC分类号： H04M1/64 , H04M1/652
CPC分类号： H04M1/652
摘要： A method, remote answering machine controller and computer program product are provided for programmable control based upon message importance. Responsive to an incoming call being received, checking a current message priority is performed. Responsive to the identified current message priority, the incoming call is answered after a dynamically programmable number of incoming rings. Then a recorded message is delivered and a caller is prompted for selected priority. The caller selected priority is identified and stored with an incoming message for the incoming call. When the owner of the remote answering machine calls to collect messages, a current highest priority of the current messages is announced. The highest priority message of the current messages is played back first. Then the owner is prompted to continue with message play back.
摘要翻译：提供了一种基于消息重要性的方法，远程应答机控制器和计算机程序产品，用于可编程控制。响应于正在接收的来电，执行当前消息优先级的检查。响应于所识别的当前消息优先级，来电在动态可编程数量的进入环之后应答。然后传送一条记录的消息，并提示一个呼叫者选择优先级。呼叫者选择的优先级被识别并存储有用于呼入呼叫的传入消息。当远程应答机的所有者呼叫收集消息时，将宣布当前消息的当前最高优先级。首先播放当前消息的最高优先级消息。然后提示所有者继续播放消息。

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