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1. 发明申请

US20060179103A1 System and method for providing a double adder for decimal floating point operations 失效
公开(公告)号：US20060179103A1
公开(公告)日：2006-08-10
申请号：US11054687
申请日：2005-02-09
申请人： Steven Carlough , Wilhelm Haller , Wen Li , Eric Schwarz
发明人： Steven Carlough , Wilhelm Haller , Wen Li , Eric Schwarz
IPC分类号： G06F7/50
CPC分类号： G06F7/4912 , G06F7/483 , G06F7/507
摘要： A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle. The system further includes an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle. In addition, a mechanism is provided for selecting between each of the sums and the sums incremented by one. The input to the mechanism includes the carry chain. The output includes the final sum of the first operand and the second operand. The selecting occurs during the second clock cycle.

2. 发明申请

US20060179090A1 System and method for converting binary to decimal 审中-公开
标题翻译：将二进制转换为十进制的系统和方法
公开(公告)号：US20060179090A1
公开(公告)日：2006-08-10
申请号：US11054232
申请日：2005-02-09
申请人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
发明人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
IPC分类号： G06F7/00
CPC分类号： H03M7/12
摘要： A method for converting from binary to decimal. The method includes receiving a binary number, the binary number including one or more sets of bits. An accumulated sum is set to zero. The accumulated sum is in a binary coded decimal (BCD) format. The following loop is repeated for each set of bits in the binary number in order from the set of bits containing the most significant bit of the binary number to the set of bits containing the least significant bit of the binary number: the accumulated sum is converted into a 5,1 code format resulting in an interim sum. The loop also includes repeating for each next bit in the set in order from the most significant bit to the least significant bit in the set: doubling the interim sum; and replacing the least significant bit of the interim sum with the next bit. The last step in the loop includes converting the interim sum into the BCD format and storing the results of the converting in the accumulated sum. Once all of the sets of bits in the binary number have been processed through the loop, the accumulated sum is output as the final result.
摘要翻译：一种从二进制转换为十进制的方法。该方法包括接收二进制数，该二进制数包括一个或多个位组。累积和设为零。累加和是二进制编码十进制（BCD）格式。从包含二进制数的最高有效位的位的集合到包含二进制数的最低有效位的位的位的顺序从二进制数中的每组位重复以下循环：累积和被转换成为5,1代码格式，产生临时总和。循环还包括从组中的最高有效位到最低有效位的顺序对集合中的每个下一个位进行重复：使中间和加倍; 并用下一位代替中间和的最低有效位。循环的最后一步包括将中间和转换为BCD格式，并将转换的结果存储在累加和中。一旦通过循环处理了二进制数的所有位组，就将输出累加和作为最终结果。

3. 发明申请

US20060179102A1 System and method for performing decimal division 失效
公开(公告)号：US20060179102A1
公开(公告)日：2006-08-10
申请号：US11055221
申请日：2005-02-10
申请人： Steven Carlough , Paulomi Kadakia , Wen Li , Eric Schwarz
发明人： Steven Carlough , Paulomi Kadakia , Wen Li , Eric Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/4917 , G06F2207/5352
摘要： A method for performing decimal division including receiving a scaled divisor and dividend and storing a subset of the multiples of the scaled divisor. An accumulated quotient is initialized to be equal to zero, a first current remainder is initialized to be equal to the scaled dividend, and a second current remainder is initialized to be equal to the scaled dividend minus the scaled divisor. The following loop is performed until a selected number of quotient digits are produced. An estimated next quotient digit is calculated based on the first digit of the first current remainder. A temp remainder is selected to be either the first current remainder or the second current remainder based on the estimated next quotient digit. A first next remainder is calculated by subtracting one of the stored multiples from the temp remainder, where the stored multiple is selected based on a first digit of the first current remainder. A second next remainder is calculated by subtracting an other one of the stored multiples from the temp remainder, where the other one of the stored multiples is selected based on the first current remainder. An actual quotient digits is calculated based on the estimated next quotient digit, the first current remainder and the first next remainder. The accumulated quotient is updated with the actual next quotient digit. Finally, the first current remainder is set to be equal to the first next remainder and the second current remainder is set to be equal to the second next remainder.

4. 发明申请

US20060179101A1 System and method for providing a decimal multiply algorithm using a double adder 失效
公开(公告)号：US20060179101A1
公开(公告)日：2006-08-10
申请号：US11054567
申请日：2005-02-09
申请人： Steven Carlough , Wen Li , Eric Schwarz
发明人： Steven Carlough , Wen Li , Eric Schwarz
IPC分类号： G06F7/52
CPC分类号： G06F7/496 , G06F2207/4911
摘要： A system for performing decimal multiplication including input registers for inputting a multiplier and a multiplicand. The multiplier includes one or more digits. The system also includes one or more two cycle adders and mechanism. The mechanism receives the multiplier and the multiplicand into the input registers. A running sum is reset to zero. The mechanism also performs for each of the digits in the multiplier in order from least significant digit to most significant digit: creating a partial product of the digit and the multiplicand; and adding the partial product to the running sum using the two cycle adders. When the loop is completed for each of the digits in the multiplier, the mechanism outputs the running sum as the result.

5. 发明申请

US20060179091A1 System and method for performing decimal to binary conversion 有权
标题翻译：用于执行十进制到二进制转换的系统和方法
公开(公告)号：US20060179091A1
公开(公告)日：2006-08-10
申请号：US11054233
申请日：2005-02-09
申请人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
发明人： Steven Carlough , Bruce Fleischer , Wen Li , Eric Schwarz
IPC分类号： G06F7/00
CPC分类号： H03M7/12
摘要： A method for converting from binary to decimal. The method includes receiving a binary coded decimal (BCD) number made up of one or more sets of three digits. A running sum and a running carry are set to zero. The following steps are performed for each set of three digits in the BCD number in order from the set of three digits containing the three most significant digits of the BCD number to the set of three digits containing the three least significant digits of the BCD number. The steps include: creating six partial products based on the set of three digits, the running sum and the running carry; combining the six partial products into two partial products; and storing the two partial products in the running sum and the running carry. After the loop has been performed for each set of three digits in the BCD number, the running sum and the running carry are combined into a final binary result.
摘要翻译：一种从二进制转换为十进制的方法。该方法包括接收由一个或多个三位数字组成的二进制编码十进制（BCD）号码。运行总和和运行进位设置为零。对于BCD号码中的每一组三位数字，按照从包含BCD号码三个最高有效数字的三位数字到包含BCD号码三个最低有效位数字的三位数组的顺序执行以下步骤。步骤包括：根据三位数字，运行总和和运行进位创建六个部分产品; 将六部分产品合并成两部分产品; 并将两个部分乘积存储在运行和运行中。在对BCD号码中的每组三位数进行了循环之后，运行总和和运行进位被组合成最终的二进制结果。

6. 发明申请

US20060179099A1 System and method for performing decimal floating point addition 失效
公开(公告)号：US20060179099A1
公开(公告)日：2006-08-10
申请号：US11055231
申请日：2005-02-10
申请人： Steven Carlough , Wen Li , Eric Schwarz
发明人： Steven Carlough , Wen Li , Eric Schwarz
IPC分类号： G06F7/38
CPC分类号： G06F7/4912 , G06F2207/4911
摘要： A method for performing a decimal floating point operation. A first operand including a first coefficient and a first exponent is received. The method also includes receiving a second operand that includes a second coefficient and a second exponent. An operation associated with the first operand and the second operand is received. The operation is an addition or a subtraction. Three concurrent calculations are performed on the first operand and the second operand. The first concurrent calculation includes applying the operation to the first operand and the second operand based on a first assumption that the first exponent is equal to the second exponent. The applying the operation based on the first assumption results in a first result and includes utilizing a two cycle adder. The second concurrent calculation includes applying the operation to the first operand and the second operand based on a second assumption that an absolute difference between the first exponent and the second exponent is less than or equal to a number of leading zeros in the coefficient of the operand with the larger exponent. The applying the operation based on the second assumption results in a second result and includes utilizing the two cycle adder. The third concurrent calculation includes applying the operation to the first operand and the second operand based on a third assumption that the absolute difference between the first exponent and the second exponent is greater than the number of leading zeros in the coefficient of the operand with the larger exponent. The applying the operation based on the third assumption results in a third result and includes utilizing the two cycle adder. A final result is selected from the first result, the second result and the third result.

7. 发明申请

US20060031279A1 Highly parallel structure for fast multi cycle binary and decimal adder unit 审中-公开
标题翻译：用于快速多周期二进制和十进制加法器单元的高度并行结构
公开(公告)号：US20060031279A1
公开(公告)日：2006-02-09
申请号：US11175489
申请日：2005-07-06
申请人： Wilhelm Haller , Wen Li , Michael Kelly , Holger Wetter
发明人： Wilhelm Haller , Wen Li , Michael Kelly , Holger Wetter
IPC分类号： G06F7/50
CPC分类号： G06F7/494 , G06F7/508 , G06F7/575 , G06F2207/4924
摘要： An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.
摘要翻译：一个加法器电路，用于将两个二进制或两个十进制操作数A和B相加，其中运算由输入操作数A和B直接计算而不加加6或减6运算到进位计算中。对于所有时序关键功能，可以使用简化的输入数据集，即有效的十进制数据，并且不需要单独的检查逻辑排除不存在的十进制数（10至15）。这降低了逻辑功能的复杂性。

8. 发明申请

US20060179098A1 System and method for reduction of leading zero detect for decimal floating point numbers 审中-公开
标题翻译：用于减小十进制浮点数的前导零检测的系统和方法
公开(公告)号：US20060179098A1
公开(公告)日：2006-08-10
申请号：US11054234
申请日：2005-02-09
申请人： Michael Kelly , Wen Li , Eric Schwarz , Wai Wong
发明人： Michael Kelly , Wen Li , Eric Schwarz , Wai Wong
IPC分类号： G06F7/38
CPC分类号： G06F7/74 , G06F7/491 , G06F2207/4911
摘要： A method for leading zero detection. The method includes receiving DPD encoded data representing a three digit BCD number and determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least one leading zero digit. A group one switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least one leading zero digit and set to one otherwise. The method also includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least two leading zero digits. A group two switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least two leading zero digits and set to one otherwise. The method further includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains three leading zero digits. A group three switch is set to zero if was determined that the BCD number represented by the DPD encoded data contains three leading zero digits and set to one otherwise.
摘要翻译：一种引导零检测的方法。如果由DPD编码数据表示的BCD数字包含至少一个前导零数字，则该方法包括接收表示三位BCD号码的DPD编码数据，并直接从DPD编码数据确定。如果确定由DPD编码数据表示的BCD数字包含至少一个前导零数字并且另外设置为一个，则将一组开关设置为零。如果由DPD编码数据表示的BCD数字包含至少两个前导零数字，则该方法还包括直接从DPD编码数据确定。如果确定由DPD编码数据表示的BCD数字包含至少两个前导零数字并且另外设置为一个，则组二开关被设置为零。如果由DPD编码数据表示的BCD数字包含三个前导零数字，则该方法还包括直接从DPD编码数据确定。如果确定由DPD编码数据表示的BCD数字包含三个前导零数字并且另外设置为一个，则组三开关被设置为零。

9. 发明授权

US09506603B2 Metal hydrides with embedded metal structures for hydrogen storage 有权
标题翻译：具有嵌入金属结构的金属氢化物用于储氢
公开(公告)号：US09506603B2
公开(公告)日：2016-11-29
申请号：US13615988
申请日：2012-09-14
申请人： Wen Li , John J. Vajo , Alan J. Jacobsen , Mei Cai , Martin P. Sulic
发明人： Wen Li , John J. Vajo , Alan J. Jacobsen , Mei Cai , Martin P. Sulic
IPC分类号： F17C11/00
CPC分类号： F17C11/005 , Y02E60/321 , Y10T29/49826
摘要： One illustrative embodiment includes materials and devices including an integrated hydrogen storage structure including a plurality of continuously connected thermally conductive elongated members, the elongated members including continuously connected openings between the elongated members; and, a metal hydride material contacting the elongated members and disposed within the connected openings and surrounding the elongated members.
摘要翻译：一个说明性实施例包括包括包括多个连续连接的导热细长构件的集成氢存储结构的材料和装置，细长构件包括在细长构件之间的连续连接的开口; 以及金属氢化物材料，其与细长构件接触并且设置在连接的开口内并围绕细长构件。

10. 发明授权

US09126834B2 Hydrogen storage materials 有权
标题翻译：储氢材料
公开(公告)号：US09126834B2
公开(公告)日：2015-09-08
申请号：US12615524
申请日：2009-11-10
申请人： Wen Li , Adam F. Gross , Alan J. Jacobsen , John J. Vajo
发明人： Wen Li , Adam F. Gross , Alan J. Jacobsen , John J. Vajo
IPC分类号： C01B31/02 , B82Y30/00 , C01B3/00 , B01J20/20 , B01J20/02
CPC分类号： C01B31/02 , B01J20/0203 , B01J20/20 , B82Y30/00 , C01B3/0021 , C01B3/0026 , C01B3/0031 , C01B3/0036 , C01B3/0042 , C01B3/0047 , C01B3/0057 , C01B3/0068 , C01B3/0084 , C01B32/05 , Y02E60/325 , Y02E60/327
摘要： A hydrogen storage material has been developed that comprises a metal hydride material embedded into a carbon microstructure that generally exhibits a greater bulk thermal conductivity than the surrounding bulk metal hydride material.
摘要翻译：已经开发了一种储氢材料，其包含嵌入到碳微结构中的金属氢化物材料，其通常表现出比周围的体金属氢化物材料更大的体积导热系数。

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