专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070115982A1 Hashing algorithm for network receive filtering 有权
标题翻译：用于网络接收过滤的哈希算法
公开(公告)号：US20070115982A1
公开(公告)日：2007-05-24
申请号：US11255124
申请日：2005-10-20
申请人： Steve Pope , Derek Roberts , David Riddoch , Ching Yu , John Chiang , Der-Ren Chu
发明人： Steve Pope , Derek Roberts , David Riddoch , Ching Yu , John Chiang , Der-Ren Chu
IPC分类号： H04L12/56
CPC分类号： G06F17/30867 , G06F17/30864 , H04L45/742 , H04L45/745 , H04L47/2441 , H04L47/621 , H04L49/90 , H04L67/10 , H04L69/16 , H04L69/161 , H04L69/162 , H04L69/163 , H04L69/164 , H04L69/22 , Y10S707/922
摘要： Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.
摘要翻译：大致描述了网络接口设备被分配最大的搜索范围。散列函数被应用于每个输入分组的报头信息，以产生分组的哈希码。哈希代码指定在其中应当找到特定头部信息的表的特定子集，并且在该子集内进行迭代搜索。如果搜索在超出搜索限制之前找到匹配的条目，则传入数据包将被传递到匹配条目中标识的接收队列。但是，如果在找到匹配的条目之前搜索达到搜索限制，则设备会将数据包传递到主机系统中的默认队列（如内核队列）。然后，内核负责将数据包传递到正确的端点。

2. 发明申请

US20060288129A1 DMA descriptor queue read and cache write pointer arrangement 有权
公开(公告)号：US20060288129A1
公开(公告)日：2006-12-21
申请号：US11156228
申请日：2005-06-17
申请人： Steve Pope , Derek Roberts , David Riddoch , Ching Yu , John Chiang , Der-Ren Chu
发明人： Steve Pope , Derek Roberts , David Riddoch , Ching Yu , John Chiang , Der-Ren Chu
IPC分类号： G06F13/28
CPC分类号： H04L49/901 , G06F13/28 , G06F13/385 , H04L49/90
摘要： Method and apparatus for retrieving buffer descriptors from a host memory for use by a peripheral device. In an embodiment, a peripheral device such as a NIC includes a plurality of buffer descriptor caches each corresponding to a respective one of a plurality of host memory descriptor queues, and a plurality of queue descriptors each corresponding to a respective one of the host memory descriptor queues. Each of the queue descriptors includes a host memory read address pointer for the corresponding descriptor queue, and this same read pointer is used to derive algorithmically the descriptor cache write addresses at which to write buffer descriptors retrieved from the corresponding host memory descriptor queue.

3. 发明申请

US20060174251A1 Transmit completion event batching 有权
公开(公告)号：US20060174251A1
公开(公告)日：2006-08-03
申请号：US11050483
申请日：2005-02-03
申请人： Steve Pope , David Riddoch , Ching Yu , Derek Roberts , John Chiang
发明人： Steve Pope , David Riddoch , Ching Yu , Derek Roberts , John Chiang
IPC分类号： G06F9/46
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901
摘要： Method for managing a data transmit queue, for use with a host and a network interface device. Roughly described, the host writes data buffer descriptors into a transmit descriptor queue, and the network interface device writes events to notify the host when it has completed processing of a transmit data buffer. Each of the transmit completion event descriptors notify the host of completion of a plurality of the transmit data buffers.

4. 发明申请

US20070174511A1 Transmit rate pacing system and method 有权
标题翻译：发送速率起搏系统及方法
公开(公告)号：US20070174511A1
公开(公告)日：2007-07-26
申请号：US11329444
申请日：2006-01-11
申请人： Ching Yu , David Riddoch , Steve Pope , John Chiang , Alok Singh , Derek Roberts
发明人： Ching Yu , David Riddoch , Steve Pope , John Chiang , Alok Singh , Derek Roberts
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： System and method of a pace engine for governing the different transmission rates tailored for different connections by rate pacing a plurality of queues are described. Roughly described, the pace engine includes a binning controller for receiving queues from a transmit DMA queue manager and determines the earliest allowed time for a particular queue that is stored and paced in a Work Bin, a Fast Bin, or a Slow Bin. A pace table stores information about the minimum inter-packet-gap for each connection that is coupled to the transmit DMA queue manager. A timer is coupled to the binning controller with a multi-bit continuous counter that increments at a predetermined time unit and wraps around after a predetermined amount of time.
摘要翻译：描述了用于通过速率起搏多个队列来为不同连接量身定制的不同传输速率的步调引擎的系统和方法。粗略地描述，速度引擎包括用于从发送DMA队列管理器接收队列的分档控制器，并且确定在工作仓，快速仓或慢速仓中存储和起搏的特定队列的最早允许时间。步速表存储关于耦合到发送DMA队列管理器的每个连接的最小间隔间隔的信息。定时器与具有多位连续计数器的分箱控制器耦合，该计数器以预定时间单位递增并在预定时间量之后卷绕。

5. 发明授权

US06529503B1 Apparatus and method for storing header information in a network switch 有权
标题翻译：在网络交换机中存储报头信息的装置和方法
公开(公告)号：US06529503B1
公开(公告)日：2003-03-04
申请号：US09315970
申请日：1999-05-21
申请人： John Chiang , Ching Yu
发明人： John Chiang , Ching Yu
IPC分类号： H04L1256
CPC分类号： H04L49/3054 , H04L49/254 , H04L49/30 , H04L49/3009 , H04L49/351 , H04L49/352 , H04L49/354 , H04L49/45
摘要： A network switch configured for switching data packets across multiple ports uses an external memory to store data frames. A scheduler controls access to the external memory based on predetermined arbitration logic. When a data frame is transmitted to the external memory, a portion of the data frame is stored on the switch for processing by decision making logic to generate frame forwarding information. The data frame is then transmitted back to the switch for transmission through the appropriate port(s) on the switch.
摘要翻译：配置为跨多个端口切换数据包的网络交换机使用外部存储器来存储数据帧。调度器基于预定的仲裁逻辑控制对外部存储器的访问。当将数据帧发送到外部存储器时，数据帧的一部分被存储在交换机上，由决策逻辑进行处理以产生帧转发信息。然后将数据帧发送回交换机，以通过交换机上的相应端口进行传输。

6. 发明授权

US06651172B1 Multi-phase EEPROM reading for network interface initialization 有权
标题翻译：用于网络接口初始化的多相EEPROM读数
公开(公告)号：US06651172B1
公开(公告)日：2003-11-18
申请号：US09321842
申请日：1999-05-28
申请人： Ching Yu , Jeffrey Dwork , John Chiang , Hung-Duy Vo
发明人： Ching Yu , Jeffrey Dwork , John Chiang , Hung-Duy Vo
IPC分类号： G06F900
CPC分类号： G06F9/4411
摘要： A novel method is provided for initializing a data processing system having registers programmable with configuration data read from a non-volatile memory at power-up. The method includes segmenting the non-volatile memory into a first portion for storing first data, and a second portion for storing second data having lower priority than the first data. The first portion is smaller than the second portion. The first data are read from the first portion to program a first group of registers. Thereafter, the second data are read from the second portion to program a second group of registers. As a result, a host is enabled to access the first group of registers, while the second data are being read from the second memory portion.
摘要翻译：提供一种新颖的方法来初始化具有可编程的寄存器的数据处理系统，该寄存器在上电时从非易失性存储器读取的配置数据可编程。该方法包括将非易失性存储器分割成用于存储第一数据的第一部分，以及用于存储具有比第一数据优先级低的第二数据的第二部分。第一部分小于第二部分。从第一部分读取第一数据以对第一组寄存器进行编程。此后，从第二部分读取第二数据以编程第二组寄存器。结果，主机能够访问第一组寄存器，而第二数据正在从第二存储器部分读取。

7. 发明授权

US06721277B1 Generic register interface for accessing registers located in different clock domains 有权
标题翻译：用于访问位于不同时钟域的寄存器的通用寄存器接口
公开(公告)号：US06721277B1
公开(公告)日：2004-04-13
申请号：US09321086
申请日：1999-05-28
申请人： Ching Yu , Jeffrey Dwork , John Chiang
发明人： Ching Yu , Jeffrey Dwork , John Chiang
IPC分类号： G01R3108
CPC分类号： G06F1/12 , H04L7/02
摘要： A novel method of providing an external host processor with access to registers located in different clock domains. The method comprises the steps of translating host processor interface signals into internal register interface signals, and performing handshaking with the registers via the internal register interface. The handshaking includes supplying registers with a register access signal for enabling access to a selected register, and producing a register ready signal in response to the register access signal. Synchronization signals delayed with respect to the register ready signal may be used for synchronizing registers located in different clock domains with the processor interface.
摘要翻译：提供外部主机处理器访问位于不同时钟域中的寄存器的新颖方法。该方法包括将主机处理器接口信号转换成内部寄存器接口信号，并通过内部寄存器接口与寄存器执行握手的步骤。握手包括向寄存器提供寄存器访问信号以使得能够访问所选择的寄存器，并且响应于寄存器访问信号产生寄存器就绪信号。相对于寄存器就绪信号延迟的同步信号可以用于与处理器接口同步位于不同时钟域的寄存器。

8. 发明申请

US20100071239A1 Illuminating sign 审中-公开
标题翻译：照亮标志
公开(公告)号：US20100071239A1
公开(公告)日：2010-03-25
申请号：US12284659
申请日：2008-09-23
申请人： David Chiang , John Chiang
发明人： David Chiang , John Chiang
IPC分类号： G09F13/06
CPC分类号： G09F13/04 , G09F13/0413 , G09F13/22 , G09F2013/1895 , G09F2013/222
摘要： An illuminating sign includes a base panel; an illuminating unit, and a front casing. The front casing includes a metallic light blocking frame attached on the base panel for enhancing a strength of the front casing, wherein the light blocking frame has a plurality of through slots spacedly formed thereon, a plurality of illuminating members securely supported in front of the base panel, and a highlighting element provided at the illuminating members, wherein when the illumination unit is operated for generating the light towards the front casing, the metallic light blocking frame not only blocks the light passing therethrough but also facilitates efficient and effective heat transfer from the illuminating unit to an exterior of the front casing for preventing the illuminating unit from being overheat within the front casing.
摘要翻译：照明标志包括基板; 照明单元和前壳体。前壳体包括安装在基板上的金属遮光框，用于增强前壳体的强度，其中遮光框架具有间隔地形成在其上的多个通孔，多个照明构件牢固地支撑在底座的前面面板和设置在照明构件上的高亮元件，其中当照明单元被操作以朝向前壳体产生光时，金属遮光框架不仅阻挡穿过其中的光，而且还有助于从照明单元到前壳体的外部，用于防止照明单元在前壳体内过热。

9. 发明授权

US06247089B1 Efficient data loading scheme to minimize PCI bus arbitrations delays and wait states 有权
标题翻译：有效的数据加载方案可以最大限度地减少PCI总线仲裁的延迟和等待状态
公开(公告)号：US06247089B1
公开(公告)日：2001-06-12
申请号：US09154076
申请日：1998-09-16
申请人： Jerry Chun-Jen Kuo , John Chiang
发明人： Jerry Chun-Jen Kuo , John Chiang
IPC分类号： G06F1300
CPC分类号： G06F13/385
摘要： A network interface has a static random access memory (SRAM) that outputs ordered data to a target by using a first and second holding register, and an output holding register. The SRAM supplies a data set to the first holding register which supplies the first data set to the second holding register. The SRAM also replenishes the first holding register with a second data set. A multiplexer selectively supplies the data set stored in one of the two holding registers to the output holding register which supplies that data set to a bus connected to the target. A bus interface unit state machine supplies a select signal to the multiplexer to control the selection between the first and second holding registers. The state machine generates the select signal based on a bus access controller detecting a target ready signal generated by the target indicating the target's readiness to receive a data set. The select signal enables the multiplexer to supply the next ordered data set to the output holding register. If the target ready signal is asserted too frequently for the first holding register to replenish the second holding register, then the state machine generates a select signal that controls the multiplexer to supply the data set stored within the first holding register to the output holding register. If the target ready signal is asserted relatively infrequently and the first holding register has sufficient time to replenish the second holding register, then the state machine generates a select signal that controls the multiplexer to supply the data set stored within the second holding register to the output holding register.
摘要翻译：网络接口具有通过使用第一和第二保持寄存器以及输出保持寄存器将有序数据输出到目标的静态随机存取存储器（SRAM）。 SRAM将数据组提供给第一保持寄存器，该第一保持寄存器将第一数据组提供给第二保持寄存器。 SRAM还用第二个数据组补充第一个保持寄存器。复用器选择性地将存储在两个保持寄存器之一中的数据组提供给输出保持寄存器，该输出保持寄存器将该数据组提供给连接到目标的总线。总线接口单元状态机向多路复用器提供选择信号以控制第一和第二保持寄存器之间的选择。状态机基于总线访问控制器产生选择信号，该总线访问控制器检测由目标产生的指示目标准备接收数据集的目标就绪信号。选择信号使复用器能够将下一个有序数据集提供给输出保持寄存器。如果对于第一保持寄存器来补偿目标就绪信号太频繁地补充第二保持寄存器，则状态机产生控制多路复用器的选择信号，以将存储在第一保持寄存器内的数据集提供给输出保持寄存器。如果目标就绪信号相对不频繁地被确定，并且第一保持寄存器具有足够的时间来补充第二保持寄存器，则状态机产生控制多路复用器以将存储在第二保持寄存器内的数据集提供给输出的选择信号持有登记册。

10. 发明授权

US07369550B1 Method and apparatus for locking a table in a network switch 失效
标题翻译：用于在网络交换机中锁定表的方法和装置
公开(公告)号：US07369550B1
公开(公告)日：2008-05-06
申请号：US10734237
申请日：2003-12-15
申请人： John Chiang
发明人： John Chiang
IPC分类号： H04L12/54 , G06F13/00 , G06F15/173
CPC分类号： H04L49/901 , H04L49/90
摘要： An apparatus and method are disclosed for locking a table within a network switch. The table is used to store entries that contain addresses of network stations connected to the network switch. A scheduler regulates access to the address table by allocating prescribed time slots during which components of the network switch can access the address table. Each component requiring access to the address table must wait until it is assigned a time slot in order to further determine if any other components are accessing the address table. If none of the other components are accessing the address table, then the component requiring access can initiate a transaction.
摘要翻译：公开了一种用于在网络交换机内锁定表的装置和方法。该表用于存储包含连接到网络交换机的网络站的地址的条目。调度器通过分配规定的时隙来调节对地址表的访问，其中网络交换机的组件可以访问地址表。需要访问地址表的每个组件必须等待它被分配一个时隙，以进一步确定是否有其他组件正在访问地址表。如果没有其他组件访问地址表，则需要访问的组件可以启动事务。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式