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1. 发明授权

US5084411A Semiconductor processing with silicon cap over Si.sub.1-x Ge.sub.x Film 失效
标题翻译：半导体处理与Si1-xGex薄膜上的硅帽
公开(公告)号：US5084411A
公开(公告)日：1992-01-28
申请号：US277593
申请日：1988-11-29
申请人： Stephen Laderman , Martin Scott , Theodore I. Kamins , Judy L. Hoyt , Clifford A. King , James F. Gibbons , David B. Noble
发明人： Stephen Laderman , Martin Scott , Theodore I. Kamins , Judy L. Hoyt , Clifford A. King , James F. Gibbons , David B. Noble
IPC分类号： H01L21/20 , H01L21/205
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/0262 , Y10S148/015 , Y10S438/902
摘要： Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si.sub.1-x Ge.sub.x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625.degree. to 1000.degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap. Some differences in the number of misfit dislocations generated in CVD and MBE films were observed after annealing uncapped layers at temperatures between 625.degree. and 825.degree. C.
摘要翻译：根据以下发现提供了具有硅到SiGe合金异质结的改进的器件。使用X射线形貌和透射电子显微镜来定量由作为化学气相沉积技术的限制反应处理（LRP）形成的生长的Si1-xGex膜中的失配位错间隔。这些分析技术也用于研究在通过LRP和分子束外延（MBE）生长的材料退火期间的位错形成。失配位错首先出现在生长材料中的厚度对于两种生长技术是相似的。在625℃至1000℃的范围内快速热退火后，还研究了封盖和未封装的膜的热稳定性。在含有外延硅帽的样品中观察到不合适的位错显着更少。在625°和825℃之间的温度下退火未封层后，观察到在CVD和MBE膜中产生的失配位错数量的一些差异。

2. 发明授权

US5256550A Fabricating a semiconductor device with strained Si.sub.1-x Ge.sub.x layer 失效
标题翻译：制造具有应变Si1-xGex层的半导体器件
公开(公告)号：US5256550A
公开(公告)日：1993-10-26
申请号：US715054
申请日：1991-06-12
申请人： Stephen Laderman , Martin Scott , Theodore I. Kamins , Judy L. Hoyt , Clifford A. King , James F. Gibbons , David B. Noble
发明人： Stephen Laderman , Martin Scott , Theodore I. Kamins , Judy L. Hoyt , Clifford A. King , James F. Gibbons , David B. Noble
IPC分类号： H01L21/20 , H01L21/205
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02631 , Y10S148/015 , Y10S438/902 , Y10S438/938
摘要： The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer.The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth. The composition of the third crystalline layer must be such that upon deposition or growth, the third layer substantially continuously binds to the heteroepitaxial structure of the second layer. Subsequent to growth of the at least three layer structure, the structure is processed at temperatures in excess of the growth temperature of the second heteroepitaxial layer. Presence of the third crystalline layer prevents the generation of a substantial amount of misfit dislocations between the first crystalline layer substrate and the second heteroepitaxial layer.
摘要翻译：本发明包括一种在应变下使用至少一个异质外延层的器件和电路的制造方法。基于先前已知的无盖层的平衡理论，异质外延层的厚度超过了在结晶衬底上的无盖异质外延层的计算的平衡临界厚度的两倍。在异质外延层的生长之后，在高于异质外延层的生长温度的温度下处理该结构。应变异质外延层（第二层）在第一底层晶体层的表面上外延生长，产生异质结。随后，在第二应变异质外延层的主要暴露表面上沉积或生长第三晶体层。第三晶体层的优选生长方式是外延生长。第三结晶层的组成必须使得在沉积或生长时，第三层基本上连续地结合到第二层的异质外延结构。在至少三层结构生长之后，在超过第二异质外延层的生长温度的温度下处理该结构。第三结晶层的存在防止在第一晶体层衬底和第二异质外延层之间产生大量的失配位错。

3. 发明申请

US20080128849A1 Low-noise semiconductor photodetectors 有权
标题翻译：低噪声半导体光电探测器
公开(公告)号：US20080128849A1
公开(公告)日：2008-06-05
申请号：US11978276
申请日：2007-10-29
申请人： Conor S. Rafferty , Clifford A. King
发明人： Conor S. Rafferty , Clifford A. King
IPC分类号： H01L31/0352 , H01L21/331
CPC分类号： H01L31/0352 , H01L27/14649 , H01L31/03529 , H01L31/101 , H01L2924/0002 , Y02E10/50 , H01L2924/00
摘要： A photodetector is formed from a body of semiconductor material substantially surrounded by dielectric surfaces. A passivation process is applied to at least one surface to reduce the rate of carrier generation and recombination on that surface. Photocurrent is read out from at least one electrical contact, which is formed on a doped region whose surface lies entirely on a passivated surface. Unwanted leakage current from un-passivated surfaces is reduced through one of the following methods. (a) The un-passivated surface is separated from the photo-collecting contact by at least two junctions (b) The un-passivated surface is doped to a very high level, at least equal to the conduction band or valence band density of states of the semiconductor (c) An accumulation or inversion layer is formed on the un-passivated surface by the application of an electric field. Electrical contacts are made to all doped regions, and bias is applied so that a reverse bias is maintained across all junctions.
摘要翻译：光电检测器由基本上被电介质表面包围的半导体材料体形成。钝化过程被应用于至少一个表面以降低载体在该表面上的产生和重组的速率。从至少一个电触点读出光电流，该电触点形成在其表面完全位于钝化表面上的掺杂区域上。通过以下方法之一减少未钝化表面的不需要的泄漏电流。（a）未钝化的表面通过至少两个结与光电收集接触分离（b）未钝化的表面被掺杂到非常高的水平，至少等于状态的导带或价带密度的半导体（c）通过施加电场在未钝化的表面上形成堆积或反转层。对所有掺杂区域进行电触点，并且施加偏压，使得跨所有接合部保持反向偏压。

4. 发明授权

US6087683A Silicon germanium heterostructure bipolar transistor with indium doped base 失效
标题翻译：硅锗异质结双极晶体管掺杂铟基
公开(公告)号：US6087683A
公开(公告)日：2000-07-11
申请号：US127373
申请日：1998-07-31
申请人： Clifford A. King , Isik C. Kizilyalli
发明人： Clifford A. King , Isik C. Kizilyalli
IPC分类号： H01L29/73 , H01L21/331 , H01L29/165 , H01L29/167 , H01L29/737 , H05B35/00
CPC分类号： H01L29/167 , H01L29/7378
摘要： The present invention provides, in one embodiment, a method of fabricating a heterostructure bipolar transistor. This particular embodiment comprises forming a n-type doped region in a semiconductor substrate to form a collector, epitaxially forming a base on the collector, epitaxially doping the base with indium while forming the base, and forming an emitter on the base. The base is epitaxially formed, and at the same time the base is doped with indium. In other words, the indium is epitaxially incorporated within the base as the base is being formed. In addition to the indium, the base may also be epitaxially doped with boron. Since, indium is incorporated into the base with the same epitaxial process used to form the base, the damage typically associated with conventional implantation processes are not present, and thus, the high annealing temperatures to repair the damage are not required. The base can be doped and formed at the same time; thereby, saving processing time.
摘要翻译：本发明在一个实施例中提供了制造异质结双极晶体管的方法。该特定实施例包括在半导体衬底中形成n型掺杂区以形成集电极，在集电极上外延形成基极，在形成基底的同时，用铟外延掺杂铟，并在基底上形成发射极。基底是外延形成的，同时基底上掺杂有铟。换句话说，当正在形成基底时，铟外延结合在基底内。除了铟之外，碱也可以外延掺杂硼。由于铟以与形成基底相同的外延工艺结合到基底中，所以不存在通常与常规注入工艺相关的损伤，因此不需要用于修复损伤的高退火温度。碱可以同时掺杂并形成; 从而节省处理时间。

5. 发明授权

US08686365B2 Imaging apparatus and methods 有权
标题翻译：成像设备和方法
公开(公告)号：US08686365B2
公开(公告)日：2014-04-01
申请号：US12510109
申请日：2009-07-27
申请人： Conor S. Rafferty , Anders Ingvar Aberg , Tirunelveli Subramaniam Sriram , Bryan D. Ackland , Clifford A. King
发明人： Conor S. Rafferty , Anders Ingvar Aberg , Tirunelveli Subramaniam Sriram , Bryan D. Ackland , Clifford A. King
IPC分类号： G01J5/02 , H01L31/0232
CPC分类号： H01L27/14627 , G01J3/02 , G01J3/0294 , G01J3/51 , G01J3/513 , H01L27/14621 , H01L27/14629 , H01L27/14632 , H01L27/14636 , H01L27/14647 , H01L27/14685
摘要： Optical imaging structures and methods are disclosed. One structure may be implemented as an imaging pixel having multiple photodetectors. The photodetectors may detect different wavelengths of incident radiation, and may be operated simultaneously or at separate times. An imager may include an imaging array of pixels of the type described. Methods of operating such structures are also described.
摘要翻译：公开了光学成像结构和方法。一个结构可以被实现为具有多个光电检测器的成像像素。光电检测器可以检测入射辐射的不同波长，并且可以同时或在不同的时间运行。成像器可以包括所述类型的像素的成像阵列。还描述了操作这种结构的方法。

6. 发明申请

US20100019154A1 IMAGING APPARATUS AND METHODS 有权
标题翻译：成像装置和方法
公开(公告)号：US20100019154A1
公开(公告)日：2010-01-28
申请号：US12510109
申请日：2009-07-27
申请人： Conor S. Rafferty , Anders Ingvar Aberg , Tirunelveli Subramaniam Sriram , Bryan D. Ackland , Clifford A. King
发明人： Conor S. Rafferty , Anders Ingvar Aberg , Tirunelveli Subramaniam Sriram , Bryan D. Ackland , Clifford A. King
IPC分类号： G01J5/02 , H01L31/0232 , H01L31/028
CPC分类号： H01L27/14627 , G01J3/02 , G01J3/0294 , G01J3/51 , G01J3/513 , H01L27/14621 , H01L27/14629 , H01L27/14632 , H01L27/14636 , H01L27/14647 , H01L27/14685
摘要： Optical imaging structures and methods are disclosed. One structure may be implemented as an imaging pixel having multiple photodetectors. The photodetectors may detect different wavelengths of incident radiation, and may be operated simultaneously or at separate times. An imager may include an imaging array of pixels of the type described. Methods of operating such structures are also described.
摘要翻译：公开了光学成像结构和方法。一个结构可以被实现为具有多个光电检测器的成像像素。光电检测器可以检测入射辐射的不同波长，并且可以同时或在不同的时间运行。成像器可以包括所述类型的像素的成像阵列。还描述了操作这种结构的方法。

7. 发明授权

US5620907A Method for making a heterojunction bipolar transistor 失效
标题翻译：制造异质结双极晶体管的方法
公开(公告)号：US5620907A
公开(公告)日：1997-04-15
申请号：US610646
申请日：1996-03-04
申请人： Bahram Jalali-Farahani , Clifford A. King
发明人： Bahram Jalali-Farahani , Clifford A. King
IPC分类号： H01L21/331 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystalline material, and contains a distribution of ion-implanted impurities. An emitter overlies the intrinsic base portion, and a spacer at least partially overlies the emitter. The spacer overhangs the extrinsic base portion by at least a distance characteristic of lateral straggle of the ion-implanted impurities.
摘要翻译：集成电路中的异质结双极晶体管具有固有和非本征基极部分。本征基本部分基本上包括外延硅 - 锗合金。外在基部基本上包括多晶材料，并且包含离子注入杂质的分布。发射极覆盖本征基极部分，并且间隔物至少部分地覆盖发射极。间隔物通过离子注入的杂质的横向偏移的至少一个距离特性突出到外部基部。

8. 发明授权

US08648948B2 Imaging systems with multiple imaging pixel types and related methods 有权
标题翻译：具有多个成像像素类型和相关方法的成像系统
公开(公告)号：US08648948B2
公开(公告)日：2014-02-11
申请号：US12570679
申请日：2009-09-30
申请人： Conor S. Rafferty , Clifford A. King , Michael Philip Decelle , Jason Y. Sproul , Bryan D. Ackland
发明人： Conor S. Rafferty , Clifford A. King , Michael Philip Decelle , Jason Y. Sproul , Bryan D. Ackland
IPC分类号： H04N5/335
CPC分类号： H04N5/35563
摘要： Imaging arrays comprising at least two different imaging pixel types are described. The different imaging pixel types may differ in their light sensitivities and/or light saturation levels. Methods of processing the output signals of the imaging arrays are also described, and may produce images having a greater dynamic range than would result from an imaging array comprising only one of the at least two different imaging pixel types.
摘要翻译：描述包括至少两个不同成像像素类型的成像阵列。不同的成像像素类型在其光敏度和/或光饱和度方面可能不同。还描述了处理成像阵列的输出信号的方法，并且可以产生具有比由仅包括至少两种不同成像像素类型中的一种的成像阵列产生的动态范围更大的图像。

9. 发明申请

US20120062774A1 ADAPTIVE SOLID STATE IMAGE SENSOR 审中-公开
标题翻译：自适应固态图像传感器
公开(公告)号：US20120062774A1
公开(公告)日：2012-03-15
申请号：US13300135
申请日：2011-11-18
申请人： Bryan D. Ackland , Clifford A. King , Conor S. Rafferty
发明人： Bryan D. Ackland , Clifford A. King , Conor S. Rafferty
IPC分类号： H04N5/335
CPC分类号： H04N5/33 , H04N5/332 , H04N9/045
摘要： An improved monolithic solid state imager comprises plural sub-arrays of respectively different kinds of pixels, an optional filter mosaic comprising color filters and clear elements, and circuitry to process the output of the pixels. The different kinds of pixels respond to respectively different spectral ranges. Advantageously the different kinds of pixels can be chosen from: 1) SWIR pixels responsive to short wavelength infrared (SWIR) in the range of approximately 800-1800 nm; 2) regular pixels responsive to visible and NIR radiation (400-1000 nm) and wideband pixels responsive to visible, NIR and SWIR radiation.
摘要翻译：改进的单片固态成像器包括分别不同种类的像素的多个子阵列，包括滤色器和清晰元件的可选滤色器马赛克，以及处理像素的输出的电路。不同种类的像素响应于不同的光谱范围。有利地，可以从以下选择不同种类的像素：1）响应于约800-1800nm范围内的短波长红外（SWIR）的SWIR像素; 2）响应于可见光和近红外辐射（400-1000nm）的响应于可见光NIR和SWIR辐射的宽带像素的规则像素。

10. 发明申请

US20120061567A1 IMAGING APPARATUS AND METHODS 有权
标题翻译：成像装置和方法
公开(公告)号：US20120061567A1
公开(公告)日：2012-03-15
申请号：US13299712
申请日：2011-11-18
申请人： Conor S. Rafferty , Anders Ingvar Aberg , Tirunelveli Subramaniam Sriram , Bryan D. Ackland , Clifford A. King
发明人： Conor S. Rafferty , Anders Ingvar Aberg , Tirunelveli Subramaniam Sriram , Bryan D. Ackland , Clifford A. King
IPC分类号： H01L27/14
CPC分类号： H01L27/14649 , H01L27/14625
摘要： Imagers, pixels, and methods of using the same are disclosed for imaging in various spectra, such as visible, near infrared (IR), and short wavelength IR (SWIR). The imager may have an imaging array having pixels of different types. The different types of pixels may detect different ranges of wavelengths in the IR, or the SWIR, spectra. The pixels may include a filter which blocks some wavelengths of radiation in the IR spectrum while passing other wavelengths. The filter may be formed of a semiconductor material, and therefore may be easily integrated with a CMOS pixel using conventional CMOS processing techniques.
摘要翻译：公开了使用它们的成像器，像素和方法用于在诸如可见光，近红外（IR）和短波长IR（SWIR）的各种光谱中成像。成像器可以具有具有不同类型的像素的成像阵列。不同类型的像素可以检测IR或SWIR光谱中的不同波长范围。像素可以包括滤光器，其在通过其它波长的同时阻挡IR光谱中的一些波长的辐射。滤波器可以由半导体材料形成，因此可以使用传统的CMOS处理技术容易地与CMOS像素集成。

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