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1. 发明申请

US20100323487A1 RADIATION HARDENED DEVICE 失效
标题翻译：辐射硬化设备
公开(公告)号：US20100323487A1
公开(公告)日：2010-12-23
申请号：US12868428
申请日：2010-08-25
申请人： Stephen J. Gaul , Michael D. Church , Brent R. Doyle
发明人： Stephen J. Gaul , Michael D. Church , Brent R. Doyle
IPC分类号： H01L21/762
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823481 , H01L29/1083
摘要： A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.
摘要翻译： “标签”MOS器件提供辐射硬度，同时支持减小栅极宽度要求。 “标签式”MOS器件还采用了机身连接环，可减少磁场阈值泄漏。在一个实现中，“标签式”MOS器件被设计成使得突片的宽度基于MOS器件的至少沟道长度，使得器件的源极和漏极区域之间的辐射诱导寄生传导路径具有电阻高于器件沟道电阻。

2. 发明申请

US20100038726A1 RADIATION HARDENED DEVICE 失效
公开(公告)号：US20100038726A1
公开(公告)日：2010-02-18
申请号：US12372893
申请日：2009-02-18
申请人： Stephen J. GAUL , Michael D. Church , Brent R. Doyle
发明人： Stephen J. GAUL , Michael D. Church , Brent R. Doyle
IPC分类号： H01L29/772 , H01L21/30
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823481 , H01L29/1083
摘要： A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.

3. 发明授权

US08268693B2 Method for fabricating a radiation hardened device 失效
标题翻译：辐射硬化装置的制造方法
公开(公告)号：US08268693B2
公开(公告)日：2012-09-18
申请号：US12868428
申请日：2010-08-25
申请人： Stephen Joseph Gaul , Michael D. Church , Brent R. Doyle
发明人： Stephen Joseph Gaul , Michael D. Church , Brent R. Doyle
IPC分类号： H01L21/336 , H01L21/332
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823481 , H01L29/1083
摘要： A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.
摘要翻译： “标签”MOS器件提供辐射硬度，同时支持减小栅极宽度要求。 “标签式”MOS器件还采用了机身连接环，可减少磁场阈值泄漏。在一个实现中，“标签式”MOS器件被设计成使得突片的宽度基于MOS器件的至少沟道长度，使得器件的源极和漏极区域之间的辐射诱导寄生传导路径具有电阻高于器件沟道电阻。

4. 发明授权

US07804143B2 Radiation hardened device 失效
标题翻译：辐射硬化装置
公开(公告)号：US07804143B2
公开(公告)日：2010-09-28
申请号：US12372893
申请日：2009-02-18
申请人： Stephen Joseph Gaul , Michael D. Church , Brent R. Doyle
发明人： Stephen Joseph Gaul , Michael D. Church , Brent R. Doyle
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823481 , H01L29/1083
摘要： A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.
摘要翻译： “标签”MOS器件提供辐射硬度，同时支持减小栅极宽度要求。 “标签式”MOS器件还采用了机身连接环，可减少磁场阈值泄漏。在一个实现中，“标签式”MOS器件被设计成使得突片的宽度基于MOS器件的至少沟道长度，使得器件的源极和漏极区域之间的辐射诱导寄生传导路径具有电阻高于器件沟道电阻。

5. 发明授权

US06507226B2 Power device driving circuit and associated methods 有权
公开(公告)号：US06507226B2
公开(公告)日：2003-01-14
申请号：US09915119
申请日：2001-07-25
申请人： James W. Swonger , Brent R. Doyle
发明人： James W. Swonger , Brent R. Doyle
IPC分类号： H03B100
CPC分类号： H03K17/063 , H03K2217/0036
摘要： The circuit and method translate a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption. The circuit for driving the power device includes a low side gate driver, and a high side gate driver adjacent thereto. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

6. 发明授权

US4682057A Circuit design technique to prevent current hogging when minimizing interconnect stripes by paralleling STL or ISL gate inputs 失效
标题翻译：电路设计技术，通过并联STL或ISL门极输入来最小化互连条纹，以防止电流偏移
公开(公告)号：US4682057A
公开(公告)日：1987-07-21
申请号：US301761
申请日：1981-09-14
申请人： Brent R. Doyle
发明人： Brent R. Doyle
IPC分类号： H03K19/091
CPC分类号： H03K19/0912 , H03K19/0915
摘要： An STL or ISL logic circuit comprising a plurality of single-input, multiple-output logic gates is provided. Each of these gates has a current source and a transistor including a base, emitter and multiple Schottky diode-to-collector contacts. The bases of the logic gate transistors are tied together to minimize metal interconnect stripes when a fanout greater than that of one gate is needed. Current hogging is reduced by an ohmic collector contact with connects the collector of each transistor together.
摘要翻译：提供了包括多个单输入多输出逻辑门的STL或ISL逻辑电路。这些栅极中的每一个具有电流源和包括基极，发射极和多个肖特基二极管至集电极触点的晶体管。当需要大于一个门的扇出时，将逻辑门晶体管的基极连接在一起以最小化金属互连条纹。通过将每个晶体管的集电极连接在一起的欧姆集电极触点来减小电流偏移。

7. 发明授权

US06653708B2 Complementary metal oxide semiconductor with improved single event performance 失效
标题翻译：具有改善的单一事件性能的互补金属氧化物半导体
公开(公告)号：US06653708B2
公开(公告)日：2003-11-25
申请号：US09918208
申请日：2001-07-30
申请人： Brent R. Doyle
发明人： Brent R. Doyle
IPC分类号： H01L2900
CPC分类号： H01L27/0921
摘要： A junction isolated Complementary Metal Oxide Semiconductor (CMOS) transistor device includes a substrate of a first conductivity type and first and second buried layers formed within the substrate and having a second conductivity type opposite from the first conductivity type. First and second well regions of respective first and second conductivity are formed above respective first and second buried layers. An NMOS transistor and PMOS transistor are formed in the respective first and second well regions. The buried layer of the NMOS transistor is at −V (typically ground) and the buried layer of the PMOS transistor is biased at a positive supply voltage and spaced sufficiently from the NMOS transistor to improve single event effects occurrence.
摘要翻译：接合隔离的互补金属氧化物半导体（CMOS）晶体管器件包括第一导电类型的衬底和形成在衬底内并具有与第一导电类型相反的第二导电类型的第一和第二掩埋层。各自的第一和第二导电性的第一和第二阱区形成在相应的第一和第二埋层之上。在相应的第一和第二阱区域中形成NMOS晶体管和PMOS晶体管。 NMOS晶体管的掩埋层处于-V（通常接地），并且PMOS晶体管的掩埋层被偏置在正电源电压并且与NMOS晶体管充分隔开以改善单个事件效应的出现。

8. 发明授权

US4891606A Photocurrent compensation using active devices 失效
标题翻译：使用有源器件进行光电流补偿
公开(公告)号：US4891606A
公开(公告)日：1990-01-02
申请号：US307944
申请日：1989-02-09
申请人： Jack E. Clark, II , Jeffrey C. Lee , Brent R. Doyle
发明人： Jack E. Clark, II , Jeffrey C. Lee , Brent R. Doyle
IPC分类号： H03F3/08
CPC分类号： H03F3/08 , H03F3/082
摘要： A current mirror having an amplification factor K providing a photocurrent compensation current to a node having a mismatch of junction photocurrent. The load device on the input leg of the current mirror has an area 1/K times the device width of the larger device junction area at the node and a device width ratio with drive device of the input leg of a current mirror equal to the ratio of mismatch J at the node.
摘要翻译：具有放大系数K的电流镜，其向具有接合光电流失配的节点提供光电流补偿电流。电流镜的输入支路上的负载装置具有节点处较大器件结区的器件宽度的1 / K倍，与电流镜的输入支路的驱动器件的器件宽度比等于该比率的不匹配J在节点。

9. 发明授权

US06563347B2 Redundant comparator design for improved offset voltage and single event effects hardness 失效
公开(公告)号：US06563347B2
公开(公告)日：2003-05-13
申请号：US09973106
申请日：2001-10-09
申请人： Brent R. Doyle , James W. Swonger
发明人： Brent R. Doyle , James W. Swonger
IPC分类号： H03K522
CPC分类号： H03K5/24
摘要： An analog comparator architecture has improved immunity to single event effects and variations in input offset voltage. A conventional single analog comparator-based circuit is replaced with plural comparators, driving a “majority vote” logic block. The effective input offset voltage of the multi-comparator design is the middle one of the individual comparators' input offset voltages. A single event upset on any comparator may momentarily perturb its output into the incorrect state; however, the output of the majority voting logic block will remain in the correct state, as only one comparator is upset. In addition, where a heavy ion strike on any comparator's bias current source causes a momentary loss of bias current, this upsets only one comparator, so that the output of the voting logic block is unaffected.

10. 发明授权

US4240846A Method of fabricating up diffused substrate FED logic utilizing a two-step epitaxial deposition 失效
标题翻译：使用两步外延沉积制造扩散衬底FED逻辑的方法
公开(公告)号：US4240846A
公开(公告)日：1980-12-23
申请号：US919632
申请日：1978-06-27
申请人： Brent R. Doyle
发明人： Brent R. Doyle
IPC分类号： H01L21/20 , H01L21/74 , H01L21/822 , H01L21/8228 , H01L27/02
CPC分类号： H01L27/0237 , H01L21/74 , H01L21/822 , H01L21/82285
摘要： A complementary pair of vertically aligned, inversely operated transistors formed from a P type substrate, a first N type epitaxial layer, a second N type epitaxial layer and a buried, updiffused P type region between the two epitaxial layers. The impurity concentration of the buried region decreases from its junction with the first epitaxial layer to its junction with the second epitaxial layer whose impurity concentration is less than that of the first epitaxial layer. High impurity concentration N type guard ring and P type base ring are diffused simultaneously with the out diffusion of the buried P type region into the second epitaxial layer. The substrate, first epitaxial layer and buried region constitute the emitter, base, and collector of the inverse vertical PNP transistor and the first epitaxial layer, buried region and second epitaxial layer constitute the emitter, base, and collector of the inverse vertical NPN transistor.
摘要翻译：在两个外延层之间由P型衬底，第一N型外延层，第二N型外延层和埋入式更新的P型区域形成的互补对垂直对准的反向操作的晶体管。掩埋区域的杂质浓度从其与第一外延层的接合到其与杂质浓度小于第一外延层的杂质浓度的第二外延层的结的下降。高杂质浓度N型保护环和P型基环与掩埋P型区域扩散到第二外延层同时扩散。衬底，第一外延层和掩埋区域构成反垂直PNP晶体管的发射极，基极和集电极，第一外延层，埋入区和第二外延层构成反向垂直NPN晶体管的发射极，基极和集电极。

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