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1. 发明授权

US5898678A Method and apparatus for using synthetic preamable signals to awaken repeater 失效
标题翻译：使用合成可预测信号唤醒中继器的方法和装置
公开(公告)号：US5898678A
公开(公告)日：1999-04-27
申请号：US719608
申请日：1996-09-25
申请人： Robert X. Jin , Eric T. West , Kathy L. Peng , Stephen F. Dreyer
发明人： Robert X. Jin , Eric T. West , Kathy L. Peng , Stephen F. Dreyer
IPC分类号： H04L12/44 , H04L5/14
CPC分类号： H04L12/44
摘要： In a 100BASE-T4 protocol network, the "carrier.sub.-- status" signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.
摘要翻译：在100BASE-T4协议网络中，消除了与第27条中继器的给定端口的PMA上的输入分组相关联的“载波状态”信号，并且消除了网络中的PMA和第27条中继器之间的直接连接通过在通过该数据接口发送分组的实际前导码信息之前的早期，通过PMA中继器数据接口将合成前导信号发送到对应于给定端口的第27条中继器。接收合成前导信号使得中继器唤醒并将合成的前同步信号重复到中继器的其他端口。反过来，其他端口变得安静，预期将从给定端口重复数据到中继器的其他端口。

2. 发明授权

US06185190B2 Method and apparatus for using synthetic preamble signals to awaken repeater 有权
标题翻译：使用合成前导信号唤醒中继器的方法和装置
公开(公告)号：US06185190B2
公开(公告)日：2001-02-06
申请号：US09240788
申请日：1999-01-27
申请人： Robert X. Jin , Eric T. West , Kathy L. Peng , Stephen F. Dreyer
发明人： Robert X. Jin , Eric T. West , Kathy L. Peng , Stephen F. Dreyer
IPC分类号： H04J314
CPC分类号： H04L12/44
摘要： In a 100BASE-T4 protocol network, the “carrier_status” signal associated with an incoming packet on a PMA of a given port of a Clause 27 repeater is obviated and a direct connection between PMAs and a Clause 27 repeater in the network is eliminated by transmitting synthetic preamble signals over the PMA-Repeater Data Interface to the Clause 27 repeater corresponding to the given port at an early time prior to the time that the actual preamble information of the packet is transmitted over that data interface. Receipt of the synthetic preamble signals causes the repeater to awaken and to repeat the synthetic preamble signals to other ports of the repeater. In turn, the other ports become quiet in anticipation of data to be repeated from the given port to the other ports of the repeater.
摘要翻译：在100BASE-T4协议网络中，消除了与第27条中继器的给定端口的PMA上的输入分组相关联的“carrier_status”信号，并且通过发送来消除PMA与第27个中继器之间的直接连接在通过该数据接口发送分组的实际前导码信息之前的早期，通过PMA中继器数据接口向与给定端口相对应的第27条中继器的合成前导信号。接收合成前导信号使得中继器唤醒并将合成的前同步信号重复到中继器的其他端口。反过来，其他端口变得安静，预期将从给定端口重复数据到中继器的其他端口。

3. 发明授权

US5768301A Apparatus and method for detecting and correcting pair swap, and implementing a link integrity function in a packet-based data communications system 失效
标题翻译：用于检测和校正配对交换的装置和方法，以及在基于分组的数据通信系统中实现链路完整性功能
公开(公告)号：US5768301A
公开(公告)日：1998-06-16
申请号：US859017
申请日：1997-05-20
申请人： Stephen F. Dreyer , Robert X. Jin , Eric T. West
发明人： Stephen F. Dreyer , Robert X. Jin , Eric T. West
IPC分类号： B01D17/00 , B01D21/26 , B01D29/11 , B01D35/02 , C10M175/00 , H04L1/24 , H04L12/26 , H04L12/413 , H04L12/44 , H04L25/06 , H04L25/14 , G06F11/00
CPC分类号： H04L25/14 , H04L1/242 , H04L12/44 , H04L25/06 , H04L12/2602 , H04L12/413 , H04L43/00 , H04L43/0823
摘要： The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry. Pair swap is corrected by switching the signals received on the swapped pairs prior to transmission or repetition to subsequent circuitry. Link integrity status is indicated via a transmitted signal.
摘要翻译：本发明允许检测和校正基于分组的数据通信系统中的某些错误条件，包括利用多信道或信号对的系统，其中所有信道或信号对不携带链路完整性信号或其他重复非数据信号。本发明的第一方面提供了相反极性的检测和校正。本发明的第二方面提供了对互换的检测和校正。本发明的第三方面提供一种链路完整性功能。检测反向极性，检测对交换和检测链路完整性利用接收到的数据包的非数据分量，独立地或与链路完整性信号或其他重复非数据信号相结合。通过在传输或重复之前将接收到的信号反相到后续电路来校正反极性。通过在发送或重复之前将交换对上接收的信号切换到后续电路来校正对交换。通过发送信号指示链路完整性状态。

4. 发明授权

US5920897A Apparatus and method for providing multiple channel clock-data alignment 失效
标题翻译：用于提供多通道时钟数据对准的装置和方法
公开(公告)号：US5920897A
公开(公告)日：1999-07-06
申请号：US693760
申请日：1996-08-07
申请人： Robert X. Jin , Eric T. West , Stephen F. Dreyer
发明人： Robert X. Jin , Eric T. West , Stephen F. Dreyer
IPC分类号： G06F13/00 , H04J3/06 , G06P13/00
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0008
摘要： An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.
摘要翻译：提供了一种用于根据单个时钟对准任意数量的数据信号的多个并行通道的装置和方法。通过使用先入先出（FIFO）原理和为每个接收到的数据信道实现FIFO原理的各个存储元件来实现同步过程。每个通道的数据信号被读入对应的存储元件，按顺序保持，并且在与指定的单个时钟信号同步的断言读出信号时读出。该装置和方法优选地使用准备从实现FIFO原理的存储元件读取的数据的指示和主时钟信号的存在，以激活从对应的存储元件读取数据。因此，每个数据通道与主时钟信号完全对齐。可以为100BASE-T4接收机实现时钟数据对准功能。

5. 发明授权

US5727006A Apparatus and method for detecting and correcting reverse polarity, in a packet-based data communications system 失效
标题翻译：在基于分组的数据通信系统中检测和校正反向极性的装置和方法
公开(公告)号：US5727006A
公开(公告)日：1998-03-10
申请号：US698374
申请日：1996-08-15
申请人： Stephen F. Dreyer , Robert X. Jin , Eric T. West
发明人： Stephen F. Dreyer , Robert X. Jin , Eric T. West
IPC分类号： B01D17/00 , B01D21/26 , B01D29/11 , B01D35/02 , C10M175/00 , H04L1/24 , H04L12/26 , H04L12/413 , H04L12/44 , H04L25/06 , H04L25/14 , G06F11/00
CPC分类号： H04L25/14 , H04L1/242 , H04L12/44 , H04L25/06 , H04L12/2602 , H04L12/413 , H04L43/00 , H04L43/0823
摘要： The present invention allows for the detection and correction of certain error conditions in packet-based data communications systems, including systems utilizing multiple channels or signal pairs, where all channels or signal pairs do not carry a link integrity signal or other repetitive non-data signal. A first aspect of the present invention provides detection and correction for reverse polarity. A second aspect of the present invention provides detection and correction for pair swap. A third aspect of the present invention provides a link integrity function. Detection of reverse polarity, detection of pair swap, and detection of link integrity by utilizes the non-data components of received packets, either independently or in conjunction with a link integrity signal or other repetitive non-data signal. Reverse polarity is corrected by inverting the received signals prior to transmission or repetition to subsequent circuitry. Pair swap is corrected by switching the signals received on the swapped pairs prior to transmission or repetition to subsequent circuitry. Link integrity status is indicated via a transmitted signal.
摘要翻译：本发明允许检测和校正基于分组的数据通信系统中的某些错误条件，包括利用多信道或信号对的系统，其中所有信道或信号对不携带链路完整性信号或其他重复非数据信号。本发明的第一方面提供了相反极性的检测和校正。本发明的第二方面提供了对互换的检测和校正。本发明的第三方面提供一种链路完整性功能。通过独立地或结合链路完整性信号或其他重复的非数据信号利用接收到的分组的非数据分量来检测反极性，检测对交换和检测链路完整性。通过在传输或重复之前将接收到的信号反相到后续电路来校正反极性。通过在发送或重复之前将交换对上接收的信号切换到后续电路来校正对交换。通过发送信号指示链路完整性状态。

6. 发明授权

US06173380B2 Apparatus and method for providing multiple channel clock-data alignment 失效
标题翻译：用于提供多通道时钟数据对准的装置和方法
公开(公告)号：US06173380B2
公开(公告)日：2001-01-09
申请号：US09118700
申请日：1998-07-16
申请人： Robert X. Jin , Eric T. West , Stephen F. Dreyer
发明人： Robert X. Jin , Eric T. West , Stephen F. Dreyer
IPC分类号： G06F1300
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0008
摘要： An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.
摘要翻译：提供了一种用于根据单个时钟对准任意数量的数据信号的多个并行通道的装置和方法。通过使用先入先出（FIFO）原理和为每个接收到的数据信道实现FIFO原理的各个存储元件来实现同步过程。每个通道的数据信号被读入对应的存储元件，按顺序保持，并且在与指定的单个时钟信号同步的断言读出信号时被读出。该装置和方法优选地使用准备从实现FIFO原理的存储元件读取的数据的指示和主时钟信号的存在，以激活从对应的存储元件读取数据。因此，每个数据通道与主时钟信号完全对齐。可以为100BASE-T4接收机实现时钟数据对准功能。

7. 发明授权

US06879187B2 Signal detect circuit for high speed data receivers 失效
标题翻译：用于高速数据接收机的信号检测电路
公开(公告)号：US06879187B2
公开(公告)日：2005-04-12
申请号：US10609802
申请日：2003-06-30
申请人： Robert X. Jin , Kathy L. Peng , Stephen F. Dreyer
发明人： Robert X. Jin , Kathy L. Peng , Stephen F. Dreyer
IPC分类号： G01R23/00 , H03K5/08 , H03K5/153 , H03K5/26 , H03K5/22
CPC分类号： G01R23/005 , H03K5/08 , H03K5/153 , H03K5/26
摘要： In accordance with one embodiment of the present invention, a signal detect circuit may analyze an input signal before passing it on to a receiver. The analysis may be done outside of the data path to avoid affecting the data path speed or adding distortion or jitter. The positive and negative thresholds of the data may be checked to see if the numbers of positive and negative crossings are comparable. Random and bursty noise can be detected since such noise normally does not have comparable positive and negative crossings.
摘要翻译：根据本发明的一个实施例，信号检测电路可以在输入信号传送到接收器之前分析输入信号。分析可以在数据路径之外进行，以避免影响数据路径速度或增加失真或抖动。可以检查数据的正和负阈值以查看正和负交叉的数量是否可比。可以检测到随机和突发噪声，因为这种噪声通常不具有可比的正负交叉。

8. 发明授权

US06614271B1 Signal detect circuit for high speed data receivers 失效
标题翻译：用于高速数据接收机的信号检测电路
公开(公告)号：US06614271B1
公开(公告)日：2003-09-02
申请号：US10171071
申请日：2002-06-13
申请人： Robert X. Jin , Kathy L. Peng , Stephen F. Dreyer
发明人： Robert X. Jin , Kathy L. Peng , Stephen F. Dreyer
IPC分类号： H03K5153
CPC分类号： G01R23/005 , H03K5/08 , H03K5/153 , H03K5/26
摘要： In accordance with one embodiment of the present invention, a signal detect circuit may analyze an input signal before passing it on to a receiver. The analysis may be done outside of the data path to avoid affecting the data path speed or adding distortion or jitter. The positive and negative thresholds of the data may be checked to see if the numbers of positive and negative crossings are comparable. Random and bursty noise can be detected since such noise normally does not have comparable positive and negative crossings.
摘要翻译：根据本发明的一个实施例，信号检测电路可以在输入信号传送到接收器之前分析输入信号。分析可以在数据路径之外进行，以避免影响数据路径速度或增加失真或抖动。可以检查数据的正和负阈值以查看正和负交叉的数量是否可比。可以检测到随机和突发噪声，因为这种噪声通常不具有可比的正负交叉。

9. 发明授权

US5912924A Bidirectional channels using common pins for transmit and receive paths 失效
标题翻译：双向通道使用通用引脚进行发送和接收路径
公开(公告)号：US5912924A
公开(公告)日：1999-06-15
申请号：US699030
申请日：1996-08-15
申请人： Stephen F. Dreyer , Lee-Chung Yiu , Robert X. Jin
发明人： Stephen F. Dreyer , Lee-Chung Yiu , Robert X. Jin
IPC分类号： H04B1/58 , H04B3/02 , H04L5/14 , H04B3/00
CPC分类号： H04B3/02 , H04B1/58 , H04L5/1423
摘要： A bidirectional communications interface employs the same path for transmitting and receiving. The bidirectional communications interface includes one two winding transformer for both transmit and receive and an integrated circuit having a transmitter and a receiver each connected to the same pair of input/output pins. The interface enables a communications node in a communications network to transmit data to and receive data from other nodes in the network.
摘要翻译：双向通信接口采用相同的发送和接收路径。双向通信接口包括一个用于发射和接收的两个绕组变压器，以及具有发射器和接收器的集成电路，每个发射器和接收器都连接到同一对输入/输出引脚。该接口使得通信网络中的通信节点能够向网络中的其他节点发送数据并从其中接收数据。

10. 发明授权

US06327309B1 Bidirection channels using common pins for transmit and receive paths 有权
标题翻译：双向通道使用通用引脚进行发送和接收路径
公开(公告)号：US06327309B1
公开(公告)日：2001-12-04
申请号：US09216501
申请日：1998-12-18
申请人： Stephen F. Dreyer , Lee-Chung Yiu , Robert X. Jin
发明人： Stephen F. Dreyer , Lee-Chung Yiu , Robert X. Jin
IPC分类号： H04B300
CPC分类号： H04B3/02 , H04B1/58 , H04L5/1423
摘要： A bidirectional communications interface employs the same path for transmitting and receiving. The bidirectional communications interface includes one two winding transformer for both transmit and receive and an integrated circuit having a transmitter and a receiver each connected to the same pair of input/output pins. The interface enables a communications node in a communications network to transmit data to and receive data from other nodes in the network.
摘要翻译：双向通信接口采用相同的发送和接收路径。双向通信接口包括一个用于发射和接收的两个绕组变压器，以及具有发射器和接收器的集成电路，每个发射器和接收器都连接到同一对输入/输出引脚。该接口使得通信网络中的通信节点能够向网络中的其他节点发送数据并从其中接收数据。

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