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    • 1. 发明授权
    • Stackable interconnection socket
    • 可堆叠互连插座
    • US5429511A
    • 1995-07-04
    • US241510
    • 1994-05-12
    • Stephen D. DelPreteDonald SantosKerry D. ArnoldThomas D. SelgasSean Crowley
    • Stephen D. DelPreteDonald SantosKerry D. ArnoldThomas D. SelgasSean Crowley
    • H05K7/10H01R13/72
    • H05K7/1023
    • A component carrier and mating system is disclosed for aligning and mating closely spaced leads of integrated circuit (IC) packages, which protects the integrated circuit packages and permits easy installation. The system is particularly adapted for aligning and mating integrated circuits which have high pin counts. A carrier assembly aligns for mating and interconnecting at least two integrated circuit packages having a plurality of leads extending from the packages. A protective shroud covers the stacked packages to maintain the packages in electrical and mechanical engagement and to assure that no damage occurs to the integrated circuit packages. In one embodiment, a first package is installed on the carrier assembly and coupled with the protective shroud to form a pre-engagement assembly, the pre-engagement assembly is then engaged with a second package mounted on a printed circuit board. An extraction tool facilitates disengagement of the assembly from the second package mounted on the printed circuit board.
    • 公开了用于对准和配合集成电路(IC)封装的紧密间隔的引线的部件载体和配合系统,其保护集成电路封装并且允许容易的安装。 该系统特别适用于对准和配对具有高引脚数的集成电路。 载体组件对准用于配合和互连至少两个具有从封装延伸的多个引线的集成电路封装。 保护罩覆盖堆叠的包装,以使包装保持电气和机械接合,并确保集成电路封装不发生损坏。 在一个实施例中,第一包装被安装在承载器组件上并与保护罩耦合以形成预接合组件,然后将预接合组件与安装在印刷电路板上的第二封装接合。 提取工具有助于组件与安装在印刷电路板上的第二封装分离。
    • 2. 发明授权
    • Stackable interconnection socket
    • 可堆叠互连插座
    • US5318451A
    • 1994-06-07
    • US8208
    • 1993-01-25
    • Stephen D. DelPreteDonald SantosKerry D. ArnoldThomas D. SelgasSean Crowley
    • Stephen D. DelPreteDonald SantosKerry D. ArnoldThomas D. SelgasSean Crowley
    • H05K7/10H01R23/72
    • H05K7/1023
    • A component carrier and mating system is disclosed for aligning and mating closely spaced leads of integrated circuit (IC) packages, which protects the integrated circuit packages and permits easy installation. The system is particularly adapted for aligning and mating integrated circuits which have high pin counts. A carrier assembly aligns for mating and interconnecting at least two integrated circuit packages having a plurality of leads extending from the packages. A protective shroud covers the stacked packages to maintain the packages in electrical and mechanical engagement and to assure that no damage occurs to the integrated circuit packages. In one embodiment, a first package is installed on the carrier assembly and coupled with the protective shroud to form a pre-engagement assembly, the pre-engagement assembly is then engaged with a second package mounted on a printed circuit board. An extraction tool facilitates disengagement of the assembly from the second package mounted on the printed circuit board.
    • 公开了用于对准和配合集成电路(IC)封装的紧密间隔的引线的部件载体和配合系统,其保护集成电路封装并且允许容易的安装。 该系统特别适用于对准和配对具有高引脚数的集成电路。 载体组件对准用于配合和互连至少两个具有从封装延伸的多个引线的集成电路封装。 保护罩覆盖堆叠的包装,以使包装保持电气和机械接合,并确保集成电路封装不发生损坏。 在一个实施例中,第一包装被安装在承载器组件上并与保护罩耦合以形成预接合组件,然后将预接合组件与安装在印刷电路板上的第二封装接合。 提取工具有助于组件与安装在印刷电路板上的第二封装分离。
    • 7. 发明申请
    • Cloud computing appliance
    • 云计算设备
    • US20110289310A1
    • 2011-11-24
    • US13112931
    • 2011-05-20
    • Thomas D. SelgasJonathan Cutrer
    • Thomas D. SelgasJonathan Cutrer
    • H04L9/00
    • H04L9/0825H04L9/0894H04L2209/60
    • A cloud computing appliance is provided in exemplary embodiment. The cloud computing device includes a computer server. The computer server is configured to receive a user file having a user filename and a user data content. The computer server is further configured to record an index record for the user file including the user filename and a dynamically generated storage name. The computer server is further configured to encipher the user data content with a symmetric key, encipher the symmetric key with an asymmetric key, and transmit a cloud file having a filename of the dynamically generated storage name and a data content of the enciphered user data content and the enciphered symmetric key.
    • 在示例性实施例中提供了云计算设备。 云计算设备包括计算机服务器。 计算机服务器被配置为接收具有用户文件名和用户数据内容的用户文件。 计算机服务器还被配置为记录用户文件的索引记录,包括用户文件名和动态生成的存储名。 计算机服务器还被配置为用对称密钥加密用户数据内容,用非对称密钥加密对称密钥,并发送具有动态生成的存储名称的文件名的云文件和加密的用户数据内容的数据内容 和加密对称密钥。
    • 9. 发明授权
    • Cache coherency without bus master arbitration signals
    • 高速缓存一致性无总线主控仲裁信号
    • US5724549A
    • 1998-03-03
    • US131043
    • 1993-10-01
    • Thomas D. SelgasThomas B. BrightmanWilliam C. Patton, Jr.
    • Thomas D. SelgasThomas B. BrightmanWilliam C. Patton, Jr.
    • G06F12/08G06F13/00
    • G06F12/0831
    • A method of data communication between asynchronous processes of a computer system is disclosed in connection with a cache coherency system for a processor-cache used in a multi-master computer system in which bus arbitration signals either are not available to the processor-cache, or are not exclusively relied on by the processor-cache to assure validity of the data in the cache (e.g., a 386-bus compatible computer system using an external secondary cache in which bus arbitration signals are only connected to and used by the secondary cache controller). In an exemplary external-chip implementation, the cache coherency system (120) comprises two PLAs--a FLUSH module (122) and a WAVESHAPING module (124). The FLUSH module (a) receives selected bus cycle definition and control signals from a microprocessor ((110), (b) detects FLUSH (cache invalidation) conditions, i.e., bus master synchronization events, and for each such FLUSH condition, (c) provides a FLUSH output signal. The WAVESHAPING module provides a corresponding CPU/FLUSH signal to the microprocessor with the appropriate set up and hold time. The exemplary bus master synchronization events, or FLUSH conditions, that cause cache invalidation are: (a) hardware generated interrupts, and (b) read or read/write accesses to I/O address space, except for those directed to a hard disk or an external coprocessor. If the bus architecture uses memory-mapped I/O, accesses to selected regions of memory-mapped I/O space could also be used. The cache coherency functionality could be implemented on-board the microprocessor.
    • 公开了一种用于计算机系统的异步过程之间的数据通信的方法,其结合用于多主计算机系统中使用的处理器 - 高速缓存一致性系统,其中总线仲裁信号对于处理器高速缓存不可用,或 不完全依赖于处理器缓存来确保缓存中的数据的有效性(例如,使用外部二级高速缓存的386总线兼容的计算机系统,其中总线仲裁信号仅连接到二级缓存控制器并由二级缓存控制器使用 )。 在示例性的外部芯片实现中,高速缓存一致性系统(120)包括两个PLA-FLUSH模块(122)和WAVESHAPING模块(124)。 FLUSH模块(a)从微处理器接收所选择的总线周期定义和控制信号((110),(b)检测FLUSH(高速缓存无效)条件,即总线主同步事件,以及每个这样的FLUSH条件,(c) 提供FLUSH输出信号,WAVESHAPING模块在相应的设置和保持时间内为微处理器提供相应的CPU / FLUSH信号,导致高速缓存无效的示例性总线主站同步事件或FLUSH条件是:(a)硬件产生 中断和(b)对I / O地址空间的读/写访问,除了定向到硬盘或外部协处理器的访问,如果总线架构使用存储器映射I / O,则访问所选择的存储区域 也可以使用映射的I / O空间。高速缓存一致性功能可以在微处理器上实现。