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1. 发明授权

US06323130B1 Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging 有权
标题翻译：使用金属硅合金自发对准形成硅化物接触的方法，用于有限的硅消耗和减少桥接
公开(公告)号：US06323130B1
公开(公告)日：2001-11-27
申请号：US09515033
申请日：2000-03-06
申请人： Stephen Bruce Brodsky , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Patricia Ann O'Neil , Yun Yu Wang
发明人： Stephen Bruce Brodsky , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Patricia Ann O'Neil , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518
摘要： A method of substantially reducing Si consumption and bridging during metal silicide contact formation comprising the steps of: (a) forming a metal silicon alloy layer over a silicon-containing substrate containing an electronic device to be electrically contacted, said silicon in said alloy layer being less than about 30 atomic % and said metal is Co, Ni or mixtures thereof; (b) annealing said metal silicon alloy layer at a temperature of from about 300° to about 500° C. so as to form a metal rich silicide layer that is substantially non-etchable compared to said metal silicon alloy or pure metal; (c) selectively removing any non-reacted metal silicon alloy over non-silicon regions; and (d) annealing said metal rich silicide layer under conditions effective in forming a metal silicide phase that is in its lowest resistance phase. An optional oxygen barrier layer may be formed over the metal silicon alloy layer prior to annealing step (b).
摘要翻译：一种在金属硅化物接触形成期间显着降低Si消耗和桥接的方法，包括以下步骤：（a）在含有电接触的电子器件的含硅衬底上形成金属硅合金层，所述合金层中的所述硅为小于约30原子％，所述金属为Co，Ni或其混合物; （b）在约300℃至约500℃的温度下退火所述金属硅合金层，以便与所述金属硅合金或纯金属相比形成基本不可蚀刻的富金属硅化物层; （c）在非硅区域上有选择地去除任何未反应的金属硅合金; 和（d）在有效形成处于其最低电阻相的金属硅化物相的条件下退火所述富金属硅化物层。可以在退火步骤（b）之前在金属硅合金层上形成任选的氧阻挡层。

2. 发明授权

US06331486B1 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 失效
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US06331486B1
公开(公告)日：2001-12-18
申请号：US09519897
申请日：2000-03-06
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L244
CPC分类号： H01L21/28518
摘要： A method of reducing contact resistance of metal silicides to a silicon-containing substrate is provided. The method includes first forming a metal germanium layer over a silicon-containing substrate. An optionally oxygen barrier layer may be formed over the metal germanium layer. Next, the structure containing the metal germanium layer is annealed at a temperature effective in converting at least a portion of the metal germanium layer into a substantially non-etchable metal silicide layer, while forming a Si-Ge interlayer between the substrate and the silicide layer. After annealing, the optional oxygen barrier layer and any remaining metal germanium layer is removed from the substrate.
摘要翻译：提供了一种降低金属硅化物与含硅衬底的接触电阻的方法。该方法包括首先在含硅衬底上形成金属锗层。可以在金属锗层上形成任选的氧阻挡层。接下来，含有金属锗层的结构在有效地将金属锗层的至少一部分转化为基本上不可蚀刻的金属硅化物层的同时，在衬底和硅化物层之间形成Si-Ge中间层的温度下进行退火。在退火之后，从衬底去除可选的氧阻挡层和任何剩余的金属锗层。

3. 发明授权

US07081676B2 Structure for controlling the interface roughness of cobalt disilicide 有权
标题翻译：控制二硅化钴界面粗糙度的结构
公开(公告)号：US07081676B2
公开(公告)日：2006-07-25
申请号：US10691299
申请日：2003-10-22
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L29/40 , H01L23/48 , H01L23/52
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

4. 发明授权

US07102234B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US07102234B2
公开(公告)日：2006-09-05
申请号：US10827064
申请日：2004-04-19
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L23/48 , H01L29/40
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

5. 发明授权

US06809030B2 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06809030B2
公开(公告)日：2004-10-26
申请号：US10185547
申请日：2002-06-28
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是含硅基体上的合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

6. 发明授权

US06753606B2 Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy 有权
标题翻译：使用金属锗合金降低金属硅化物的接触电阻的方法和结构
公开(公告)号：US06753606B2
公开(公告)日：2004-06-22
申请号：US09994954
申请日：2001-11-27
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Ronnen Andrew Roy , Yun Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/28518
摘要： A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g., Co—Ge or Ti—Ge, two annealing steps are required to provide the lowest resistance phase of those metals, whereas, when Ni is employed, a single annealing step forms the lowest resistance phase of Ni silicide.
摘要翻译：一种降低金属硅化物与衬底的p +硅区域或n +硅区域的接触电阻的方法，包括：（a）在含硅衬底上形成金属锗（Ge）层，其中所述金属选自由Co，Ti，Ni及其混合物组成的组; （b）任选地在所述金属锗层上形成氧阻隔层; （c）在有效地将其至少一部分转化成基本上不可蚀刻的金属硅化物层的温度下退火所述金属锗层，同时在所述含硅衬底和所述基本上不可蚀刻的衬底之间形成Si-Ge中间层金属硅化物层; 和（d）去除所述任选的氧气阻挡层和任何剩余的合金层。当使用Co或Ti合金时，例如Co-Ge或Ti-Ge，需要两个退火步骤来提供这些金属的最低电阻相，而在使用Ni时，单个退火步骤形成最低的电阻相的Ni硅化物。

7. 发明授权

US06440851B1 Method and structure for controlling the interface roughness of cobalt disilicide 失效
标题翻译：控制二硅化钴界面粗糙度的方法和结构
公开(公告)号：US06440851B1
公开(公告)日：2002-08-27
申请号：US09416083
申请日：1999-10-12
申请人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
发明人： Paul David Agnello , Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Christian Lavoie , Kirk David Peterson , Robert Joseph Purtell , Ronnen Andrew Roy , Jean Louise Jordan-Sweet , Yun Yu Wang
IPC分类号： H01L2144
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additive, over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.
摘要翻译：本文公开了一种制造具有降低的界面粗糙度的电接触以及电接触本身的方法。本发明的方法包括（a）在含硅基材上形成具有式MX的合金层，其中M是选自Co和Ni的金属，X是合金添加剂; （b）任选地在所述合金层上形成任选的氧阻隔层; （c）在足以在所述结构中形成MXSi层的温度下退火所述合金层; （d）除去所述任选的氧气阻挡层和任何剩余的合金层; 以及任选地（e）在足以在所述结构中形成MXSi 2层的温度下退火所述MXSi层。

8. 发明授权

US06413859B1 Method and structure for retarding high temperature agglomeration of silicides using alloys 失效
标题翻译：使用合金阻止硅化物高温聚集的方法和结构
公开(公告)号：US06413859B1
公开(公告)日：2002-07-02
申请号：US09519898
申请日：2000-03-06
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Paul Michael Kozlowski , Christian Lavoie , Joseph Scott Newbury , Ronnen Andrew Roy
IPC分类号： H01L214763
CPC分类号： H01L21/28518 , H01L21/823814
摘要： Complementary metal oxide semiconductor (CMOS) devices having metal silicide contacts that withstand the high temperature anneals used in activating the source/drain regions of the devices are provided by adding at least one alloying element to an initial metal layer used in forming the silicide.
摘要翻译：通过向用于形成硅化物的初始金属层添加至少一种合金元素，提供具有金属硅化物接触的互补金属氧化物半导体（CMOS）器件，其具有经受用于激活器件的源极/漏极区域的高温退火。

9. 发明授权

US06503641B2 Interconnects with Ti-containing liners 有权
标题翻译：与含Ti衬板互连
公开(公告)号：US06503641B2
公开(公告)日：2003-01-07
申请号：US09740089
申请日：2000-12-18
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Chao-Kun Hu , Kim Yang Lee , Ismail Cevdet Noyan , Robert Rosenberg , Thomas McCarroll Shaw
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , James McKell Edwin Harper , Chao-Kun Hu , Kim Yang Lee , Ismail Cevdet Noyan , Robert Rosenberg , Thomas McCarroll Shaw
IPC分类号： B32B1501
CPC分类号： H01L21/76843 , B32B15/01 , C22C27/02 , H01L21/76846 , H01L23/53223 , H01L23/53238 , H01L2924/0002 , Y10S428/929 , Y10S428/935 , Y10S428/936 , Y10S428/938 , Y10T428/12639 , Y10T428/12743 , Y10T428/12806 , Y10T428/12812 , Y10T428/12819 , Y10T428/12826 , Y10T428/12833 , Y10T428/1284 , Y10T428/12903 , H01L2924/00
摘要： An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1−XTix, Ta1−X, Hfx, Ta1−X, Inxy, Ta1−XSnx, Ta1−XZrx.
摘要翻译：公开了一种用于电子结构的电导体，其包括由合金构成的导体，该合金包括选自Ti，Zr，In，Sn中的元素的约0.001原子％至约2原子％，以及 Hf; 以及与包括Ta，W，Ti，Nb和V的合金形成的导体本体的衬垫。本发明还公开了一种用于半导体互连的衬垫，其由选自Ti ，Hf，In，Sn，Zr及其合金，TiCu3，Ta1-XTix，Ta1-X，Hfx，Ta1-X，Inxy，Ta1-XSnx，Ta1-XZrx。

10. 发明授权

US06187679B1 Low temperature formation of low resistivity titanium silicide 失效
标题翻译：低电阻率硅化钛的低温形成
公开(公告)号：US06187679B1
公开(公告)日：2001-02-13
申请号：US08807739
申请日：1997-02-26
申请人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
发明人： Cyril Cabral, Jr. , Lawrence Alfred Clevenger , Francois Max d'Heurle , James McKell Edwin Harper , Randy William Mann , Glen Lester Miles , James Spiros Nakos , Ronnen Andrew Roy , Katherine L. Saenger
IPC分类号： H01L2144
CPC分类号： C30B1/02 , C30B29/10 , H01L21/28518 , H01L29/665
摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.
摘要翻译：低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600-700℃之间

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