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1. 发明申请

US20070157006A1 Method and apparatus for microarchitecture partitioning of execution clusters 有权
标题翻译：执行集群的微架构划分方法和装置
公开(公告)号：US20070157006A1
公开(公告)日：2007-07-05
申请号：US11322768
申请日：2005-12-30
申请人： Stephan Jourdan , Avinash Sodani , Alexandre Farcy , Per Hammarlund , Sebastien Hily , Mark Davis
发明人： Stephan Jourdan , Avinash Sodani , Alexandre Farcy , Per Hammarlund , Sebastien Hily , Mark Davis
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3012 , G06F9/3828 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To the other set of micro-operations execution resources are allocated from a cluster of execution resources that can perform branching operations but not memory access operations. The first and second sets of micro-operations may be executed out of sequential order but are retired to represent their sequential instruction ordering.
摘要翻译：微架构策略和结构分区执行资源集群。在公开的微架构实施例中，表示顺序指令排序的微操作被划分成两组。对于一组微操作执行资源从可执行存储器访问操作而不是分支操作的执行资源集群分配。对另一组微操作执行资源从可执行分支操作而不是存储器访问操作的执行资源集群分配。第一组和第二组微操作可以按顺序执行，但是退休以表示其顺序指令排序。

2. 发明申请

US20070130448A1 Stack tracker 审中-公开
标题翻译：堆栈跟踪器
公开(公告)号：US20070130448A1
公开(公告)日：2007-06-07
申请号：US11291378
申请日：2005-12-01
申请人： Stephan Jourdan , Mark Davis , Sebastien Hily
发明人： Stephan Jourdan , Mark Davis , Sebastien Hily
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30043 , G06F9/30134 , G06F9/3017 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： Methods and apparatus to identify memory communications are described. In one embodiment, an access to a stack pointer is monitored, e.g., to maintain a stack tracker structure. The information stored in the stack tracker structure may be utilized to generate a distance value corresponding to a relative distance between a load instruction and a previous store instruction.
摘要翻译：描述了识别存储器通信的方法和装置。在一个实施例中，监视对堆栈指针的访问，例如，以维持堆栈跟踪器结构。存储在堆栈跟踪器结构中的信息可以用于产生对应于加载指令和先前存储指令之间的相对距离的距离值。

3. 发明申请

US20050138295A1 Apparatus and method for store address for store address prefetch and line locking 有权
标题翻译：用于存储地址预取和线路锁定的存储地址的装置和方法
公开(公告)号：US20050138295A1
公开(公告)日：2005-06-23
申请号：US10743134
申请日：2003-12-23
申请人： Per Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
发明人： Per Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
IPC分类号： G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译：本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或从高速缓冲存储器中被逐出，则重置状态位。

4. 发明申请

US20070156990A1 Load mechanism 有权
标题翻译：负载机制
公开(公告)号：US20070156990A1
公开(公告)日：2007-07-05
申请号：US11323000
申请日：2005-12-30
申请人： Per Hammarlund , Stephan Jourdan , Michael Fetterman , Glenn Hinton , Sebastien Hily , Ronak Singhal
发明人： Per Hammarlund , Stephan Jourdan , Michael Fetterman , Glenn Hinton , Sebastien Hily , Ronak Singhal
IPC分类号： G06F13/00
CPC分类号： G06F9/30043 , G06F9/30032
摘要： A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.
摘要翻译：公开了一种方法。该方法包括将加载操作调度至少是由存储器件支持的最大访问大小的两倍，将加载操作划分成具有等于存储器设备支持的最大访问大小的多个单独的加载操作段，以及执行多个加载操作段中的每一个。公开了一种另外的方法，其中使用临时寄存器来最小化用于支持未对齐访问的存储器访问的数量。

5. 发明授权

US07457932B2 Load mechanism 有权
标题翻译：负载机制
公开(公告)号：US07457932B2
公开(公告)日：2008-11-25
申请号：US11323000
申请日：2005-12-30
申请人： Per Hammarlund , Stephan Jourdan , Michael Fetterman , Glenn Hinton , Sebastien Hily , Ronak Singhal
发明人： Per Hammarlund , Stephan Jourdan , Michael Fetterman , Glenn Hinton , Sebastien Hily , Ronak Singhal
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/30032
摘要： A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.
摘要翻译：公开了一种方法。该方法包括将加载操作调度至少是由存储器件支持的最大访问大小的两倍，将加载操作划分成具有等于存储器设备支持的最大访问大小的多个单独的加载操作段，以及执行多个加载操作段中的每一个。公开了一种另外的方法，其中使用临时寄存器来最小化用于支持未对齐访问的存储器访问的数量。

6. 发明申请

US20080059753A1 Scheduling operations corresponding to store instructions 审中-公开
标题翻译：与存储指令对应的调度操作
公开(公告)号：US20080059753A1
公开(公告)日：2008-03-06
申请号：US11512819
申请日：2006-08-30
申请人： Sebastien Hily , Zhongying Zhang , Ranjani Iyer , Stephan Jourdan , Per Hammarlund
发明人： Sebastien Hily , Zhongying Zhang , Ranjani Iyer , Stephan Jourdan , Per Hammarlund
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3857
摘要： Methods and apparatus to redispatch an operation for execution in a processor are described. In one embodiment, a virtual address corresponding to a store instruction may be reselected for translation into a physical address in response to remaining unselected during a previous selection process. Other embodiments are also described.
摘要翻译：描述用于重新分配在处理器中执行的操作的方法和装置。在一个实施例中，对应于存储指令的虚拟地址可以被重新选择用于响应于在先前的选择过程期间未被选择而被翻译成物理地址。还描述了其它实施例。

7. 发明申请

US20080072019A1 Technique to clear bogus instructions from a processor pipeline 审中-公开
标题翻译：从处理器管道中清除伪造指令的技术
公开(公告)号：US20080072019A1
公开(公告)日：2008-03-20
申请号：US11523930
申请日：2006-09-19
申请人： Avinash Sodani , Ranjani Iyer , Sean Mirkes , Sebastien Hily , David Koufaty , Stephan Jourdan , Zhongying Zhang
发明人： Avinash Sodani , Ranjani Iyer , Sean Mirkes , Sebastien Hily , David Koufaty , Stephan Jourdan , Zhongying Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3861 , G06F9/3885
摘要： A technique to filter bogus instructions from a processor pipeline. At least one embodiment of the invention detects a bogus event, removes only instructions from the processor corresponding to the bogus event without affecting instructions not corresponding to the bogus event.
摘要翻译：一种从处理器管道中过滤虚假指令的技术。本发明的至少一个实施例检测虚假事件，仅移除来自与假冒事件对应的处理器的指令，而不影响不对应于虚假事件的指令。

8. 发明授权

US07130965B2 Apparatus and method for store address for store address prefetch and line locking 有权
标题翻译：用于存储地址预取和线路锁定的存储地址的装置和方法
公开(公告)号：US07130965B2
公开(公告)日：2006-10-31
申请号：US10743134
申请日：2003-12-23
申请人： Per H. Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
发明人： Per H. Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译：本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或者从高速缓冲存储器中被逐出，则重置状态位。

9. 发明申请

US20050149702A1 Method and system for memory renaming 有权
标题翻译：用于内存重命名的方法和系统
公开(公告)号：US20050149702A1
公开(公告)日：2005-07-07
申请号：US10745700
申请日：2003-12-29
申请人： Sebastien Hily , Per Hammarlund , Avinash Sodani
发明人： Sebastien Hily , Per Hammarlund , Avinash Sodani
IPC分类号： G06F9/00 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/3017 , G06F9/384 , G06F9/3861
摘要： Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted to be memory renamed, the load instruction may have a predicted store identifier associated with the load instruction. The decode unit may transform the load instruction that is predicted to be memory renamed into a data move instruction and a load check instruction. The data move instruction may read data from the cache based on the predicted store identifier and load check instruction may compare an identifier associated with an identified source store with the predicted store identifier. A retirement unit may retire the load instruction if the predicted store identifier matches an identifier associated with the identified source store. In another embodiment of the present invention, the processor may re-execute the load instruction without memory renaming if the predicted store identifier does not match the identifier associated with the identified source store.
摘要翻译：本发明的实施例提供了一种用于存储器重命名的方法，装置和系统。在一个实施例中，解码单元可以解码加载指令。如果加载指令被预测为存储器重新命名，则加载指令可以具有与加载指令相关联的预测存储标识符。解码单元可以将预测为被重命名的存储器的加载指令变换为数据移动指令和加载检查指令。数据移动指令可以基于预测的存储标识符从高速缓存读取数据，并且加载检查指令可以将与所识别的源存储器相关联的标识符与预测的存储标识符进行比较。如果预测的商店标识符与与所标识的源商店相关联的标识符匹配，则退休单元可以退出加载指令。在本发明的另一个实施例中，如果预测的存储标识符与与所识别的源存储器相关联的标识符不匹配，则处理器可以重新执行加载指令而不进行存储器重命名。

10. 发明授权

US07752423B2 Avoiding execution of instructions in a second processor by committing results obtained from speculative execution of the instructions in a first processor 失效
标题翻译：通过在第一处理器中提交从推测性执行指令获得的结果来避免在第二处理器中执行指令
公开(公告)号：US07752423B2
公开(公告)日：2010-07-06
申请号：US09896526
申请日：2001-06-28
申请人： Haitham Akkary , Sebastien Hily
发明人： Haitham Akkary , Sebastien Hily
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857
摘要： A device is presented including a first processor and a second processor. A number of memory devices are connected to the first processor and the second processor. A register buffer is connected to the first processor and the second processor. A trace buffer is connected to the first processor and the second processor. A number of memory instruction buffers are connected to the first processor and the second processor. The first processor and the second processor perform single threaded applications using multithreading resources. A method is also presented where a first thread is executed from a first processor. The first thread is also executed from a second processor as directed by the first processor. The second processor executes instructions ahead of the first processor.
摘要翻译：呈现包括第一处理器和第二处理器的设备。多个存储器件连接到第一处理器和第二处理器。寄存器缓冲器连接到第一处理器和第二处理器。跟踪缓冲器连接到第一处理器和第二处理器。多个存储器指令缓冲器连接到第一处理器和第二处理器。第一个处理器和第二个处理器使用多线程资源执行单线程应用程序。还提出了一种从第一处理器执行第一线程的方法。如第一处理器所指示的那样，第一线程也从第二处理器执行。第二处理器在第一处理器之前执行指令。

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