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1. 发明申请

US20050138295A1 Apparatus and method for store address for store address prefetch and line locking 有权
标题翻译：用于存储地址预取和线路锁定的存储地址的装置和方法
公开(公告)号：US20050138295A1
公开(公告)日：2005-06-23
申请号：US10743134
申请日：2003-12-23
申请人： Per Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
发明人： Per Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
IPC分类号： G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译：本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或从高速缓冲存储器中被逐出，则重置状态位。

2. 发明申请

US20070156990A1 Load mechanism 有权
标题翻译：负载机制
公开(公告)号：US20070156990A1
公开(公告)日：2007-07-05
申请号：US11323000
申请日：2005-12-30
申请人： Per Hammarlund , Stephan Jourdan , Michael Fetterman , Glenn Hinton , Sebastien Hily , Ronak Singhal
发明人： Per Hammarlund , Stephan Jourdan , Michael Fetterman , Glenn Hinton , Sebastien Hily , Ronak Singhal
IPC分类号： G06F13/00
CPC分类号： G06F9/30043 , G06F9/30032
摘要： A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.
摘要翻译：公开了一种方法。该方法包括将加载操作调度至少是由存储器件支持的最大访问大小的两倍，将加载操作划分成具有等于存储器设备支持的最大访问大小的多个单独的加载操作段，以及执行多个加载操作段中的每一个。公开了一种另外的方法，其中使用临时寄存器来最小化用于支持未对齐访问的存储器访问的数量。

3. 发明授权

US07457932B2 Load mechanism 有权
标题翻译：负载机制
公开(公告)号：US07457932B2
公开(公告)日：2008-11-25
申请号：US11323000
申请日：2005-12-30
申请人： Per Hammarlund , Stephan Jourdan , Michael Fetterman , Glenn Hinton , Sebastien Hily , Ronak Singhal
发明人： Per Hammarlund , Stephan Jourdan , Michael Fetterman , Glenn Hinton , Sebastien Hily , Ronak Singhal
IPC分类号： G06F12/00
CPC分类号： G06F9/30043 , G06F9/30032
摘要： A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.
摘要翻译：公开了一种方法。该方法包括将加载操作调度至少是由存储器件支持的最大访问大小的两倍，将加载操作划分成具有等于存储器设备支持的最大访问大小的多个单独的加载操作段，以及执行多个加载操作段中的每一个。公开了一种另外的方法，其中使用临时寄存器来最小化用于支持未对齐访问的存储器访问的数量。

4. 发明申请

US20070157006A1 Method and apparatus for microarchitecture partitioning of execution clusters 有权
标题翻译：执行集群的微架构划分方法和装置
公开(公告)号：US20070157006A1
公开(公告)日：2007-07-05
申请号：US11322768
申请日：2005-12-30
申请人： Stephan Jourdan , Avinash Sodani , Alexandre Farcy , Per Hammarlund , Sebastien Hily , Mark Davis
发明人： Stephan Jourdan , Avinash Sodani , Alexandre Farcy , Per Hammarlund , Sebastien Hily , Mark Davis
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3012 , G06F9/3828 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To the other set of micro-operations execution resources are allocated from a cluster of execution resources that can perform branching operations but not memory access operations. The first and second sets of micro-operations may be executed out of sequential order but are retired to represent their sequential instruction ordering.
摘要翻译：微架构策略和结构分区执行资源集群。在公开的微架构实施例中，表示顺序指令排序的微操作被划分成两组。对于一组微操作执行资源从可执行存储器访问操作而不是分支操作的执行资源集群分配。对另一组微操作执行资源从可执行分支操作而不是存储器访问操作的执行资源集群分配。第一组和第二组微操作可以按顺序执行，但是退休以表示其顺序指令排序。

5. 发明申请

US20080059753A1 Scheduling operations corresponding to store instructions 审中-公开
标题翻译：与存储指令对应的调度操作
公开(公告)号：US20080059753A1
公开(公告)日：2008-03-06
申请号：US11512819
申请日：2006-08-30
申请人： Sebastien Hily , Zhongying Zhang , Ranjani Iyer , Stephan Jourdan , Per Hammarlund
发明人： Sebastien Hily , Zhongying Zhang , Ranjani Iyer , Stephan Jourdan , Per Hammarlund
IPC分类号： G06F12/00
CPC分类号： G06F12/10 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3857
摘要： Methods and apparatus to redispatch an operation for execution in a processor are described. In one embodiment, a virtual address corresponding to a store instruction may be reselected for translation into a physical address in response to remaining unselected during a previous selection process. Other embodiments are also described.
摘要翻译：描述用于重新分配在处理器中执行的操作的方法和装置。在一个实施例中，对应于存储指令的虚拟地址可以被重新选择用于响应于在先前的选择过程期间未被选择而被翻译成物理地址。还描述了其它实施例。

6. 发明授权

US07085889B2 Use of a context identifier in a cache memory 有权
公开(公告)号：US07085889B2
公开(公告)日：2006-08-01
申请号：US10104815
申请日：2002-03-22
申请人： Per Hammarlund , Aravindh Baktha , Michael D Upton , Venkat K. S. Venkatraman
发明人： Per Hammarlund , Aravindh Baktha , Michael D Upton , Venkat K. S. Venkatraman
IPC分类号： G06F12/00
CPC分类号： G06F12/0842
摘要： A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.

7. 发明申请

US20050149702A1 Method and system for memory renaming 有权
标题翻译：用于内存重命名的方法和系统
公开(公告)号：US20050149702A1
公开(公告)日：2005-07-07
申请号：US10745700
申请日：2003-12-29
申请人： Sebastien Hily , Per Hammarlund , Avinash Sodani
发明人： Sebastien Hily , Per Hammarlund , Avinash Sodani
IPC分类号： G06F9/00 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/30043 , G06F9/3017 , G06F9/384 , G06F9/3861
摘要： Embodiments of the present invention provide a method, apparatus and system for memory renaming. In one embodiment, a decode unit may decode a load instruction. If the load instruction is predicted to be memory renamed, the load instruction may have a predicted store identifier associated with the load instruction. The decode unit may transform the load instruction that is predicted to be memory renamed into a data move instruction and a load check instruction. The data move instruction may read data from the cache based on the predicted store identifier and load check instruction may compare an identifier associated with an identified source store with the predicted store identifier. A retirement unit may retire the load instruction if the predicted store identifier matches an identifier associated with the identified source store. In another embodiment of the present invention, the processor may re-execute the load instruction without memory renaming if the predicted store identifier does not match the identifier associated with the identified source store.
摘要翻译：本发明的实施例提供了一种用于存储器重命名的方法，装置和系统。在一个实施例中，解码单元可以解码加载指令。如果加载指令被预测为存储器重新命名，则加载指令可以具有与加载指令相关联的预测存储标识符。解码单元可以将预测为被重命名的存储器的加载指令变换为数据移动指令和加载检查指令。数据移动指令可以基于预测的存储标识符从高速缓存读取数据，并且加载检查指令可以将与所识别的源存储器相关联的标识符与预测的存储标识符进行比较。如果预测的商店标识符与与所标识的源商店相关联的标识符匹配，则退休单元可以退出加载指令。在本发明的另一个实施例中，如果预测的存储标识符与与所识别的源存储器相关联的标识符不匹配，则处理器可以重新执行加载指令而不进行存储器重命名。

8. 发明授权

US07516313B2 Predicting contention in a processor 失效
标题翻译：预测处理器中的争用
公开(公告)号：US07516313B2
公开(公告)日：2009-04-07
申请号：US11027392
申请日：2004-12-29
申请人： Bratin Saha , Matthew C. Merten , Sebastien Hily , David A. Koufaty , Per Hammarlund
发明人： Bratin Saha , Matthew C. Merten , Sebastien Hily , David A. Koufaty , Per Hammarlund
IPC分类号： G06F13/376 , G06F9/38 , G06F13/18
CPC分类号： G06F9/3851 , G06F9/526
摘要： In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于预测在程序中要执行的操作的竞争的预测器。可以基于预测的结果来处理该操作，该结果可以基于多个独立的预测。在一个实施例中，如果没有预测到争用，则可以优化操作。描述和要求保护其他实施例。

9. 发明申请

US20050138339A1 Method for and a trailing store buffer for use in memory renaming 失效
标题翻译：用于存储器重命名的方法和后端存储缓冲区
公开(公告)号：US20050138339A1
公开(公告)日：2005-06-23
申请号：US10743422
申请日：2003-12-23
申请人： Sebastien Hily , Per Hammarlund
发明人： Sebastien Hily , Per Hammarlund
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3834
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient memory renaming. The method includes computing a store address, writing the store address in a first storage, writing data associated with the store address to a memory, and de-allocating the store address from the first storage, allocating the store address in a second storage, predicting a load instruction to be memory renamed, computing a load store source index, computing a load address, disambiguating the memory renamed load instruction, and retiring the memory renamed load instruction, if the store instruction is still allocated in at least one of the first storage and the second storage and should have effectively provided to the load the full data. The method may also include re-executing the load instruction without memory renaming, if the store instruction is not in at the first storage or in the second storage.
摘要翻译：本发明的实施例涉及一种能够实现高效存储器重命名的存储器管理方案和装置。该方法包括计算存储地址，将存储地址写入第一存储器中，将与存储地址相关联的数据写入存储器，以及从第一存储器解除存储地址，在第二存储器中分配存储地址，预测存储地址如果所述存储指令仍被分配在所述第一存储器中的至少一个中，则存储指令被重新命名为存储器重命名的加载指令，计算加载存储源索引，计算加载地址，消除所述存储器重命名的加载指令，以及退出所述存储器重命名加载指令，并且第二个存储应该有效地提供给负载的完整数据。如果存储指令不在第一存储器或第二存储器中，则该方法还可以包括重新执行加载指令而不进行存储器重命名。

10. 发明授权

US07475225B2 Method and apparatus for microarchitecture partitioning of execution clusters 有权
标题翻译：执行集群的微架构划分方法和装置
公开(公告)号：US07475225B2
公开(公告)日：2009-01-06
申请号：US11322768
申请日：2005-12-30
申请人： Stephan J. Jourdan , Avinash Sodani , Alexandre J. Farcy , Per Hammarlund , Sebastien Hily , Mark C. Davis
发明人： Stephan J. Jourdan , Avinash Sodani , Alexandre J. Farcy , Per Hammarlund , Sebastien Hily , Mark C. Davis
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/30101 , G06F9/3012 , G06F9/3828 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3855 , G06F9/3857 , G06F9/3885 , G06F9/3891
摘要： Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To the other set of micro-operations execution resources are allocated from a cluster of execution resources that can perform branching operations but not memory access operations. The first and second sets of micro-operations may be executed out of sequential order but are retired to represent their sequential instruction ordering.
摘要翻译：微架构策略和结构分区执行资源集群。在公开的微架构实施例中，表示顺序指令排序的微操作被划分成两组。对于一组微操作执行资源从可执行存储器访问操作而不是分支操作的执行资源集群分配。对另一组微操作执行资源从可执行分支操作而不是存储器访问操作的执行资源集群分配。第一组和第二组微操作可以按顺序执行，但是退休以表示其顺序指令排序。

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