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1. 发明申请

US20120279952A1 Thermal Treatment of Flash Memories 有权
标题翻译：闪存的热处理
公开(公告)号：US20120279952A1
公开(公告)日：2012-11-08
申请号：US13101322
申请日：2011-05-05
申请人： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
发明人： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
IPC分类号： H05B3/00
CPC分类号： G11C16/26 , G11C11/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , H01L23/345 , H01L2924/0002 , H05B3/00 , H01L2924/00
摘要： A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.
摘要翻译：存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。如果需要，加热后，可以刷新存储器。在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。

2. 发明授权

US08958242B2 Thermal treatment of flash memories 有权
标题翻译：闪存的热处理
公开(公告)号：US08958242B2
公开(公告)日：2015-02-17
申请号：US13101322
申请日：2011-05-05
申请人： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
发明人： Gian Pietro Vanalli , Stefano Corno , Giovanni Campardo , Angelo Visconti , Silvia Beltrami , Alexey Petrushin
IPC分类号： G11C11/34 , H05B3/00 , G11C11/00 , G11C16/34 , H01L23/34
CPC分类号： G11C16/26 , G11C11/00 , G11C16/3418 , G11C16/3427 , G11C16/3431 , H01L23/345 , H01L2924/0002 , H05B3/00 , H01L2924/00
摘要： A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be refreshed. In non-battery powered systems, data may be removed from the memory prior to heating and restored to the memory after heating.
摘要翻译：存储器控制器可以向闪存中的加热器提供电流以减少循环引起的误差。如果需要，加热后，可以刷新存储器。在非电池供电系统中，数据可能在加热之前从存储器中移除，并在加热后恢复到存储器。

3. 发明申请

US20080068890A1 Nand flash memory with reduced programming disturbance 有权
标题翻译： Nand闪存，减少编程干扰
公开(公告)号：US20080068890A1
公开(公告)日：2008-03-20
申请号：US11901596
申请日：2007-09-17
申请人： Silvia Beltrami , Angelo Visconti
发明人： Silvia Beltrami , Angelo Visconti
IPC分类号： G11C16/02
CPC分类号： G11C7/02 , G11C5/063 , G11C16/0483 , G11C16/12
摘要： An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.
摘要翻译：具有NAND架构的闪速存储器件的实施例，包括每个具有可编程阈值电压的数据存储单元矩阵，其中所述矩阵被布置成多个行和列，每行的存储单元连接到对应的字线和每列的存储单元被布置在多个存储单元串中，每个串中的存储单元串联连接，每列的串耦合到参考电压分配线，该参考电压分配线通过第一选择器的装置，其中每个串还包括插入在所述串的所述存储单元和所述第一选择器之间的至少一个第一屏蔽元件，所述第一屏蔽元件适于屏蔽所述存储器单元与操作中出现的电场在存储单元串和第一选择器之间。

4. 发明申请

US20130033937A1 METHODS FOR PROGRAM VERIFYING A MEMORY CELL AND MEMORY DEVICES CONFIGURED TO PERFORM THE SAME 有权
标题翻译：用于程序验证存储器单元的方法和配置为执行其的存储器件
公开(公告)号：US20130033937A1
公开(公告)日：2013-02-07
申请号：US13204029
申请日：2011-08-05
申请人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
发明人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell.
摘要翻译：公开了一种用于程序验证的方法，例如可以确定已经用编程电压偏置的存储器单元的阈值电压并且可以确定其与多个程序验证电压范围的关系的方法。程序验证阈值电压所在的电压范围决定后续的位线电压。随后的位线电压可以小于用于对存储器单元进行编程的先前位线电压。

5. 发明申请

US20120224430A1 READING MEMORY CELL HISTORY DURING PROGRAM OPERATION FOR ADAPTIVE PROGRAMMING 有权
标题翻译：在自适应编程程序运行期间读取存储单元历史
公开(公告)号：US20120224430A1
公开(公告)日：2012-09-06
申请号：US13040200
申请日：2011-03-03
申请人： Angelo Visconti , Mattia Robustelli , Silvia Beltrami , Laura Czeppel , Massimo Bertuccio
发明人： Angelo Visconti , Mattia Robustelli , Silvia Beltrami , Laura Czeppel , Massimo Bertuccio
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3495 , G11C16/0483 , G11C16/10 , G11C16/3459
摘要： Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.
摘要翻译：本文公开的主题涉及存储器件，更具体地涉及写入存储器件的性能。

6. 发明授权

US07710778B2 NAND flash memory with reduced programming disturbance 有权
标题翻译： NAND闪存具有减少的编程干扰
公开(公告)号：US07710778B2
公开(公告)日：2010-05-04
申请号：US11901596
申请日：2007-09-17
申请人： Silvia Beltrami , Angelo Visconti
发明人： Silvia Beltrami , Angelo Visconti
IPC分类号： G11C11/34
CPC分类号： G11C7/02 , G11C5/063 , G11C16/0483 , G11C16/12
摘要： An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.
摘要翻译：具有NAND架构的闪速存储器件的实施例，包括每个具有可编程阈值电压的数据存储单元矩阵，其中所述矩阵被布置成多个行和列，每行的存储单元连接到对应的字线和每列的存储单元被布置在多个存储单元串中，每个串中的存储单元串联连接，每列的串耦合到参考电压分配线，该参考电压分配线通过第一选择器的装置，其中每个串还包括插入在所述串的所述存储单元和所述第一选择器之间的至少一个第一屏蔽元件，所述第一屏蔽元件适于屏蔽所述存储器单元与操作中出现的电场在存储单元串和第一选择器之间。

7. 发明授权

US08451662B2 Reading memory cell history during program operation for adaptive programming 有权
公开(公告)号：US08451662B2
公开(公告)日：2013-05-28
申请号：US13040200
申请日：2011-03-03
申请人： Angelo Visconti , Mattia Robustelli , Silvia Beltrami , Laura Czeppel , Massimo Bertuccio
发明人： Angelo Visconti , Mattia Robustelli , Silvia Beltrami , Laura Czeppel , Massimo Bertuccio
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3495 , G11C16/0483 , G11C16/10 , G11C16/3459
摘要： Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a memory device.

8. 发明授权

US08755229B1 Limiting flash memory over programming 有权
标题翻译：通过编程限制闪存
公开(公告)号：US08755229B1
公开(公告)日：2014-06-17
申请号：US12490002
申请日：2009-06-23
申请人： Silvia Beltrami , Angelo Visconti
发明人： Silvia Beltrami , Angelo Visconti
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/12 , G11C16/3459 , G11C16/3463 , G11C16/3468 , G11C16/3486 , G11C16/3495
摘要： Certain aspects of this disclosure relate to programming an at least one flash memory cell using an at least one programming pulse with a new programming voltage having a level. The level is maintained in at least one page in a block of a flash memory controller memory, wherein the level varies as a function of a number of programming cycles applied to the at least one flash memory cell.
摘要翻译：本公开的某些方面涉及使用具有具有电平的新编程电压的至少一个编程脉冲来编程至少一个闪存单元。该电平被维持在闪速存储器控制器存储器的块中的至少一个页面中，其中该电平根据应用于至少一个闪存单元的编程周期的数量而变化。

9. 发明授权

US08670273B2 Methods for program verifying a memory cell and memory devices configured to perform the same 有权
标题翻译：用于程序验证被配置为执行相同的存储器单元和存储器件的方法
公开(公告)号：US08670273B2
公开(公告)日：2014-03-11
申请号：US13204029
申请日：2011-08-05
申请人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
发明人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： A method for program verify is disclosed, such as one in which a threshold voltage of a memory cell that has been biased with a programming voltage can be determined and its relationship with multiple program verify voltage ranges can be determined. The program verify voltage range in which the threshold voltage is located determines the subsequent bit line voltage. The subsequent bit line voltage may be less than a previous bit line voltage used to program the memory cell.
摘要翻译：公开了一种用于程序验证的方法，例如可以确定已经用编程电压偏置的存储器单元的阈值电压并且可以确定其与多个程序验证电压范围的关系的方法。程序验证阈值电压所在的电压范围决定后续的位线电压。随后的位线电压可以小于用于对存储器单元进行编程的先前位线电压。

10. 发明授权

US08619475B2 Methods to operate a memory cell 有权
标题翻译：操作存储单元的方法
公开(公告)号：US08619475B2
公开(公告)日：2013-12-31
申请号：US13204014
申请日：2011-08-05
申请人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
发明人： Seiichi Aritome , Soojin Wi , Angelo Visconti , Silvia Beltrami , Christian Monzio Compagnoni , Alessandro Sottocornola Spinelli
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C11/5628 , G11C16/3459
摘要： Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels.
摘要翻译：公开了用于操作存储器单元的存储器件和方法，诸如使用两个程序验证电平（例如，低程序验证电平和程序验证电平）来确定如何增加数据线电压的方法。确定已经用编程电压偏置的存储单元的阈值电压，并确定其与两个程序验证电平的关系。如果阈值电压小于低编程验证电平，则可以将数据线偏置在接地电压（例如0V）以用于随后的编程脉冲。如果阈值电压大于程序验证电平，则数据线可以被偏置在用于后续编程脉冲的禁止电压。如果阈值电压在两个程序验证电平之间，则对于其中阈值电压在两个程序验证电平之间的每个后续编程脉冲，可以增加数据线电压。

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