专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050253638A1 Method and circuit arrangement for resetting an integrated circuit 有权
标题翻译：用于复位集成电路的方法和电路装置
公开(公告)号：US20050253638A1
公开(公告)日：2005-11-17
申请号：US11117736
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrogmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrogmeier
IPC分类号： G06F1/24 , G11C5/14 , G11C11/4072 , H01L21/82 , H03K5/1534 , H03L7/00
CPC分类号： G06F1/24 , H03K5/1534
摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.
摘要翻译：本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

2. 发明授权

US6028815A Integrated memory 有权
标题翻译：集成内存
公开(公告)号：US6028815A
公开(公告)日：2000-02-22
申请号：US258940
申请日：1999-03-01
申请人： Sabine Schoniger , Peter Schrogmeier , Thomas Hein , Stefan Dietrich
发明人： Sabine Schoniger , Peter Schrogmeier , Thomas Hein , Stefan Dietrich
IPC分类号： G11C7/10 , G11C8/00 , G11C8/14
CPC分类号： G11C7/1006 , G11C8/00 , G11C8/14
摘要： The integrated memory has byte selection lines for selecting all the bit lines of a respective byte, as well as masking signals that are allocated to the respective byte of at least one word. In addition, the memory has a column decoder with outputs which are connected to the word selection lines, each of which, when addressed, causes all the byte selection lines for one of the words to be simultaneously selected if none of the masking signals are active. The masking signals, when activated, prevent the addressed word selection line from selecting the byte selection lines, allocated to a corresponding byte, for a corresponding word.
摘要翻译：集成存储器具有用于选择相应字节的所有位线的字节选择线以及分配给至少一个字的相应字节的屏蔽信号。此外，存储器具有列解码器，其具有连接到字选择线的输出，每个字选择线在寻址时都使得如果没有一个屏蔽信号有效则同时选择一个字的所有字节选择线。屏蔽信号被激活时，防止寻址字选择线选择分配给相应字节的字节选择线作为相应字。

3. 发明授权

US6144590A Semiconductor memory having differential bit lines 有权
标题翻译：具有差分位线的半导体存储器
公开(公告)号：US6144590A
公开(公告)日：2000-11-07
申请号：US315328
申请日：1999-05-20
申请人： Michael Markert , Musa Saglam , Sabine Schoniger , Peter Schrogmeier , Stefan Dietrich , Thomas Hein , Thilo Marx
发明人： Michael Markert , Musa Saglam , Sabine Schoniger , Peter Schrogmeier , Stefan Dietrich , Thomas Hein , Thilo Marx
IPC分类号： G11C7/18 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/18 , G11C11/4097
摘要： In a semiconductor memory, bit lines are disposed in such a way that in each case two inverted and two non-inverted bit lines lie next to one another. Adjacent switching transistors for connecting the bit lines to an inverted or a non-inverted collective line are connected to the corresponding collective line by a common contact. An advantage in terms of area is afforded by the fact that the two switching transistors have a common doping region.
摘要翻译：在半导体存储器中，位线设置成使得在每种情况下，两个反相和两个非反相位线彼此相邻。用于将位线连接到反相或非反相集合线的相邻开关晶体管通过公共接触连接到相应的集合线。由于两个开关晶体管具有共同的掺杂区域，因此在面积方面具有优点。

4. 发明授权

US06101141A Integrated memory 有权
标题翻译：集成内存
公开(公告)号：US06101141A
公开(公告)日：2000-08-08
申请号：US344922
申请日：1999-06-28
申请人： Sabine Schoniger , Peter Schrogmeier , Thomas Hein , Stefan Dietrich , Thilo Marx
发明人： Sabine Schoniger , Peter Schrogmeier , Thomas Hein , Stefan Dietrich , Thilo Marx
IPC分类号： G11C11/409 , G11C7/06 , G11C7/10 , G11C11/4096 , G11C7/02
CPC分类号： G11C7/1048 , G11C11/4096 , G11C7/1006
摘要： The integrated memory has a data line pair, which is connected to a bit line pair via at least one differential amplifier. In addition, it has a control unit for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cells, and for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells. Furthermore, it has a detector unit having two inputs connected to the data line pair. The detector unit initiates a specific control function when the second potential state of the data line pair occurs.
摘要翻译：集成存储器具有数据线对，其经由至少一个差分放大器连接到位线对。此外，它具有控制单元，用于设置数据线对上对应于要写入存储单元的数据的差分信号的第一电位状态，并且在数据线对上设置至少一个第二电位状态不对应于要写入存储单元的任何数据。此外，它具有检测器单元，其具有连接到数据线对的两个输入。当发生数据线对的第二电位状态时，检测器单元启动特定的控制功能。

5. 发明申请

US20050270852A1 Read latency control circuit 有权
标题翻译：读延迟控制电路
公开(公告)号：US20050270852A1
公开(公告)日：2005-12-08
申请号：US11136712
申请日：2005-05-25
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
IPC分类号： G06F3/06 , G11C7/22 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译：本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。本发明还提供了一种用于执行该方法的相应电路装置。

6. 发明授权

US06480024B2 Circuit configuration for programming a delay in a signal path 有权
公开(公告)号：US06480024B2
公开(公告)日：2002-11-12
申请号：US10046395
申请日：2001-10-19
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Michael Markert , Thilo Marx , Torsten Partsch , Sabine Schöniger Kieser , Peter Schrögmeier , Michael Sommer , Christian Weis
IPC分类号： H03K190173
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03K2005/00091
摘要： A circuit configuration includes two signal path sections that are used to program the delay of a signal path, in particular in DRAMs. The two signal path sections have different delays and can be driven in parallel at the input end. The two signal path sections can be connected to an output terminal via a multiplexer. A selection circuit includes two signal path sections which are connected between supply voltage potentials. The selection circuit has two complimentary transistors which are connected in series and has source-end programmable elements. These transistors can be driven by complimentary control signals. This permits the delay to be programmed flexibly with little expenditure on circuitry.

7. 发明授权

US07363561B2 Method and circuit arrangement for resetting an integrated circuit 有权
标题翻译：用于复位集成电路的方法和电路装置
公开(公告)号：US07363561B2
公开(公告)日：2008-04-22
申请号：US11117736
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrögmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrögmeier
IPC分类号： G01R31/28
CPC分类号： G06F1/24 , H03K5/1534
摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.
摘要翻译：本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

8. 发明授权

US06670802B2 Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits 有权
公开(公告)号：US06670802B2
公开(公告)日：2003-12-30
申请号：US10033131
申请日：2001-10-22
申请人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schroegmeier , Christian Weis
IPC分类号： G01R3102
CPC分类号： G11C29/003
摘要： Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

9. 发明授权

US06532188B2 Integrated memory having a row access controller for activating and deactivating row lines 有权
公开(公告)号：US06532188B2
公开(公告)日：2003-03-11
申请号：US10012161
申请日：2001-10-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch , Sabine Kieser , Peter Schroegmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch , Sabine Kieser , Peter Schroegmeier , Michael Sommer , Christian Weis
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/10 , G11C8/18
摘要： An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.

10. 发明授权

US07404018B2 Read latency control circuit 有权
标题翻译：读延迟控制电路
公开(公告)号：US07404018B2
公开(公告)日：2008-07-22
申请号：US11136712
申请日：2005-05-25
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schroegmeier
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/20 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C2207/2272
摘要： The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.
摘要翻译：本发明提供了一种用于通过用于对半导体存储器的读取访问的基于FIFO的读延迟控制电路来设置和控制读延迟（L）的方法，具有提供公共内部时钟信号的方法步骤; 从公共时钟信号产生与第一时钟信号不同的内部第一时钟信号和内部第二时钟信号; 产生用于从所述第一时钟信号读出读取数据的输出指针; 生成用于从所述第二时钟信号读取所述读取数据的输入指针; 通过在输出指针和输入指针之间分配定义的，固定地预定的时间偏移来初始化输入和输出指针。本发明还提供了一种用于执行该方法的相应电路装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式