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1. 发明申请

US20080001639A1 Device for Utilization With the Synchronization of Clock Signals, and Clock Signal Synchronizing Method 失效
标题翻译：使用时钟信号同步和时钟信号同步方法的设备
公开(公告)号：US20080001639A1
公开(公告)日：2008-01-03
申请号：US10574117
申请日：2004-09-10
申请人： Rao Rajashekhar , Alessandro Minzoni , Musa Saglam
发明人： Rao Rajashekhar , Alessandro Minzoni , Musa Saglam
IPC分类号： G06F1/10 , H03L7/06
CPC分类号： G06F1/10 , G11C7/1072 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/107
摘要： A clock signal synchronizing method and an apparatus device for utilization with the synchronization of clock signals is disclosed. In one embodiment, the apparatus includes a delay device with a variably controllable delay time into which a clock signal, or a signal obtained therefrom, is input, charged with the variably controllable delay time, and output as a delayed clock signal.A device is provided for determining whether a clock edge of the delayed clock signal output by the delay device, or of a signal obtained therefrom, lies within a predetermined time window before a corresponding clock edge of the clock signal, or of the signal obtained therefrom.
摘要翻译：公开了一种利用时钟信号同步的时钟信号同步方法和装置装置。在一个实施例中，该装置包括具有可变可控延迟时间的延迟装置，其中输入时钟信号或从其获得的信号，以可变可控延迟时间充电并输出为延迟时钟信号。提供一种装置，用于确定由延迟装置输出的延迟时钟信号的时钟边缘或由其获得的信号的时钟边缘是否位于时钟信号的相应时钟边缘之前的预定时间窗口内，或者从其获得的信号。

2. 发明申请

US20050218954A1 Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device 有权
标题翻译：可集成的，可控制的延迟装置，延迟装置的使用，以及用于延迟装置的可积分多路复用器
公开(公告)号：US20050218954A1
公开(公告)日：2005-10-06
申请号：US11077374
申请日：2005-03-11
申请人： Patrick Heyne , Musa Saglam
发明人： Patrick Heyne , Musa Saglam
IPC分类号： G11C11/407 , H03H11/26 , H03K5/00 , H03K5/13 , H03K5/14
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00156 , H03K2005/00208
摘要： A delay device has series-connected multiplexers in a differential form. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal to be delayed can be supplied. A control signal controls the switch setting of one of the multiplexers such that its output is connected to the input of the delay device. The other multiplexers have the other switch setting. In consequence, a specific delay time is set for the delay device. The multiplexers have four current paths which are coupled in pairs. One of the current path pairs can be decoupled from the current source via a transistor.
摘要翻译：延迟装置具有差分形式的串联多路复用器。多路复用器的第一连接连接到上游多路复用器的输出端。多路复用器的第二输入端连接到可被提供延迟信号的输入端。控制信号控制多路复用器之一的开关设置，使得其输出连接到延迟装置的输入端。其他多路复用器具有另一个开关设置。因此，为延迟装置设定特定的延迟时间。多路复用器具有成对耦合的四个电流路径。电流路径对之一可以通过晶体管与电流源解耦。

3. 发明授权

US6144590A Semiconductor memory having differential bit lines 有权
标题翻译：具有差分位线的半导体存储器
公开(公告)号：US6144590A
公开(公告)日：2000-11-07
申请号：US315328
申请日：1999-05-20
申请人： Michael Markert , Musa Saglam , Sabine Schoniger , Peter Schrogmeier , Stefan Dietrich , Thomas Hein , Thilo Marx
发明人： Michael Markert , Musa Saglam , Sabine Schoniger , Peter Schrogmeier , Stefan Dietrich , Thomas Hein , Thilo Marx
IPC分类号： G11C7/18 , G11C11/4097 , G11C7/00
CPC分类号： G11C7/18 , G11C11/4097
摘要： In a semiconductor memory, bit lines are disposed in such a way that in each case two inverted and two non-inverted bit lines lie next to one another. Adjacent switching transistors for connecting the bit lines to an inverted or a non-inverted collective line are connected to the corresponding collective line by a common contact. An advantage in terms of area is afforded by the fact that the two switching transistors have a common doping region.
摘要翻译：在半导体存储器中，位线设置成使得在每种情况下，两个反相和两个非反相位线彼此相邻。用于将位线连接到反相或非反相集合线的相邻开关晶体管通过公共接触连接到相应的集合线。由于两个开关晶体管具有共同的掺杂区域，因此在面积方面具有优点。

4. 发明授权

US06437410B1 Integrated memory 有权
标题翻译：集成内存
公开(公告)号：US06437410B1
公开(公告)日：2002-08-20
申请号：US09603749
申请日：2000-06-26
申请人： Stefan Dietrich , Musa Saglam , Peter Schrögmeier , Michael Markert , Sabine Schöniger , Christian Weis
发明人： Stefan Dietrich , Musa Saglam , Peter Schrögmeier , Michael Markert , Sabine Schöniger , Christian Weis
IPC分类号： H01L2976
CPC分类号： G11C7/1066 , G11C8/00 , G11C8/10
摘要： The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.
摘要翻译：集成存储器具有第一地址路径，通过该第一地址路径，地址端子连接到第一组的第一选择线并且具有对应的第一行和第一解码器电路。此外，集成存储器具有第二地址路径，通过该第二地址路径，地址端子连接到第二组的第一选择线并具有对应的第二线和第二解码器电路。第一解码器电路比第二解码器电路快。第一行具有比第二行更长的信号传播时间。

5. 发明授权

US07471129B2 Device for utilization with the synchronization of clock signals, and clock signal synchronizing method 失效
标题翻译：利用时钟信号同步的设备和时钟信号同步方法
公开(公告)号：US07471129B2
公开(公告)日：2008-12-30
申请号：US10574117
申请日：2004-09-10
申请人： Rao Rajashekhar , Alessandro Minzoni , Musa Saglam
发明人： Rao Rajashekhar , Alessandro Minzoni , Musa Saglam
IPC分类号： H03L7/06
CPC分类号： G06F1/10 , G11C7/1072 , G11C7/222 , H03L7/0814 , H03L7/0818 , H03L7/107
摘要： A clock signal synchronization method and an apparatus device for utilization with the synchronization of clock signals is disclosed. In one embodiment the apparatus includes a delay device with a variably controllable delay time into which a clock signal, or a signal obtained therefrom, is input, charged with the variably controllable delay time, and output as a delayed clock signal. A device is provided for determining whether a clock edge of the delayed clock signal output by the delay device, or of a signal obtained therefrom, lies within a predetermined time window before a corresponding clock edge of the clock signal, or of the signal obtained therefrom.
摘要翻译：公开了一种利用时钟信号同步的时钟信号同步方法和装置装置。在一个实施例中，该装置包括具有可变可控延迟时间的延迟装置，其中输入时钟信号或从其获得的信号，用可变可控延迟时间充电并输出为延迟时钟信号。提供一种装置，用于确定由延迟装置输出的延迟时钟信号的时钟边缘或由其获得的信号的时钟边缘是否位于时钟信号的相应时钟边缘之前的预定时间窗口内，或者从其获得的信号。

6. 发明申请

US20070085598A1 Integrated semiconductor circuit comprising a voltage pump and method for operating an integrated semiconductor circuit comprising a voltage pump 审中-公开
标题翻译：包括电压泵的集成半导体电路和用于操作包括电压泵的集成半导体电路的方法
公开(公告)号：US20070085598A1
公开(公告)日：2007-04-19
申请号：US11544307
申请日：2006-10-06
申请人： Musa Saglam , Kai Schiller
发明人： Musa Saglam , Kai Schiller
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： A semiconductor circuit includes a voltage pump, which has a series circuit of capacitors. The voltage pump furthermore has first switching elements, which are coupled between, in each case, two capacitors of the series circuit, and are coupled to capacitor electrodes of the capacitors by coupling lines. Connection lines are coupled to a respective connecting line and, in each case, have a second switching element, which enables an interruption of the respective connection line. It is possible for the second switching elements to be jointly switched to a conducting state when all the first switching elements are switched to a non-conducting state, as a result of which each capacitor is electrically charged individually by in each case two connection lines. It is also possible for the first switching elements to be jointly switched to a conducting state when all the second switching elements are switched to a non-conducting state, as a result of which all the electrically charged capacitors are electrically connected to one another.
摘要翻译：半导体电路包括具有电容器串联电路的电压泵。电压泵还具有第一开关元件，其在每种情况下都耦合在串联电路的两个电容器中，并且通过耦合线耦合到电容器的电容器电极。连接线耦合到相应的连接线，并且在每种情况下都具有第二开关元件，其能够中断相应的连接线。当所有第一开关元件被切换到非导通状态时，第二开关元件可能共同切换到导通状态，结果，每个电容器在每种情况下通过两条连接线单独地充电。当所有第二开关元件都切换到非导通状态时，第一开关元件也可以共同切换到导通状态，其结果是所有带电荷的电容器彼此电连接。

7. 发明授权

US07126401B2 Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device 有权
标题翻译：可集成的，可控制的延迟装置，延迟装置的使用，以及用于延迟装置的可积分多路复用器
公开(公告)号：US07126401B2
公开(公告)日：2006-10-24
申请号：US11077374
申请日：2005-03-11
申请人： Patrick Heyne , Musa Saglam
发明人： Patrick Heyne , Musa Saglam
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00156 , H03K2005/00208
摘要： A delay device has series-connected multiplexers in a differential form. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal to be delayed can be supplied. A control signal controls the switch setting of one of the multiplexers such that its output is connected to the input of the delay device. The other multiplexers have the other switch setting. In consequence, a specific delay time is set for the delay device. The multiplexers have four current paths which are coupled in pairs. One of the current path pairs can be decoupled from the current source via a transistor.
摘要翻译：延迟装置具有差分形式的串联多路复用器。多路复用器的第一连接连接到上游多路复用器的输出端。多路复用器的第二输入端连接到可被提供延迟信号的输入端。控制信号控制多路复用器之一的开关设置，使得其输出连接到延迟装置的输入端。其他多路复用器具有另一个开关设置。因此，为延迟装置设定特定的延迟时间。多路复用器具有成对耦合的四个电流路径。电流路径对之一可以通过晶体管与电流源解耦。

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