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1. 发明授权

US07084029B2 Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor 失效
标题翻译：在半导体衬底中制造空穴沟槽存储电容器的方法和空穴沟槽存储电容器
公开(公告)号：US07084029B2
公开(公告)日：2006-08-01
申请号：US10948574
申请日：2004-09-24
申请人： Srivatsa Kundalgurki , Dietmar Temmler , Hans-Peter Moll , Joerg Wiedemann
发明人： Srivatsa Kundalgurki , Dietmar Temmler , Hans-Peter Moll , Joerg Wiedemann
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10867 , H01L27/10873
摘要： To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.
摘要翻译：为了制造在半导体衬底中形成有形成在孔沟中的内部电极和在电极部中形成的包围下部的孔沟的外部电极的空穴沟槽存储电容器，内部电极继续在半导体衬底的衬底表面上方。然后，通过外延工艺将扩大半导体衬底的附加层生长到衬底表面上。在原始基板表面上形成内电极和绝缘套环的至少一部分的接触连接的过渡表面，从而增加可用于电荷存储的空穴沟槽存储电容器的表面积的尺寸而对于用于形成孔沟槽的蚀刻使用相同的纵横比。

2. 发明申请

US20050093049A1 Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor 失效
标题翻译：在半导体衬底中制造空穴沟槽存储电容器的方法和空穴沟槽存储电容器
公开(公告)号：US20050093049A1
公开(公告)日：2005-05-05
申请号：US10948574
申请日：2004-09-24
申请人： Srivatsa Kundalgurki , Dietmar Temmler , Hans-Peter Moll , Joerg Wiedemann
发明人： Srivatsa Kundalgurki , Dietmar Temmler , Hans-Peter Moll , Joerg Wiedemann
IPC分类号： H01L21/20 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10861 , H01L27/10867 , H01L27/10873
摘要： To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.
摘要翻译：为了制造在半导体衬底中形成有形成在孔沟中的内部电极和在电极部中形成的包围下部的孔沟的外部电极的空穴沟槽存储电容器，内部电极继续在半导体衬底的衬底表面上方。然后，通过外延工艺将扩大半导体衬底的附加层生长到衬底表面上。在原始基板表面上形成内电极和绝缘套环的至少一部分的接触连接的过渡表面，从而增加可用于电荷存储的空穴沟槽存储电容器的表面积的尺寸而对于用于形成孔沟槽的蚀刻使用相同的纵横比。

3. 发明授权

US07754579B2 Method of forming a semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US07754579B2
公开(公告)日：2010-07-13
申请号：US11507647
申请日：2006-08-21
申请人： Kimberly Wilson , Hans-Peter Moll , Rolf Weis , Phillip Stopford , Frank Ludwig
发明人： Kimberly Wilson , Hans-Peter Moll , Rolf Weis , Phillip Stopford , Frank Ludwig
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , Y10S438/942 , Y10S438/952
摘要： A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5), thereby forming at least a first and a second isolation trench (11a, 11b) extending along the lateral direction (X).
摘要翻译：一种形成半导体器件的方法包括在衬底部分（2）上沉积填充材料（4）和设置在衬底（1）上并具有位于衬底部分上方的开口（10）的介电层（3）（2），去除设置在电介质层（3）上方的填充材料（4），从而在开口（10）内留下介电层（3）的暴露的顶表面（6）和残余填充材料（15）在所述介电层（3）的暴露的顶表面（6）和所述残留填充材料（15）上形成硬掩模材料（5），对所述硬掩模材料（5）进行图案化以形成硬掩模（25），所述硬掩模材料（25）沿着横向方向（X）延伸的沟槽（8a，8b）和暴露与电介质层（3）相邻的残余填充材料（15）的部分和与残余填充材料（15）相邻的介电层（3）的部分），各向异性蚀刻介电层（3），残留填充材料（15）和基板（1）从而形成至少沿横向（X）延伸的第一和第二隔离沟槽（11a，11b）。

4. 发明授权

US06964912B2 Method for fabricating a semiconductor structure 失效
标题翻译：半导体结构的制造方法
公开(公告)号：US06964912B2
公开(公告)日：2005-11-15
申请号：US10721752
申请日：2003-11-26
申请人： Dirk Efferenn , Hans-Peter Moll
发明人： Dirk Efferenn , Hans-Peter Moll
IPC分类号： H01L21/76 , H01L21/8239 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10867
摘要： A method for fabricating a semiconductor structure includes providing a semiconductor substrate, providing a plurality of trenches in the semiconductor substrate using a first hard mask, and causing the hard mask to recede by a predetermined distance with respect to the trench wall at the top side of the semiconductor substrate for forming a first hard mask that has been caused to recede. An isolation trench structure is provided in the semiconductor substrate using a second hard mask, the isolation trench structure subdividing the first first hard mask that has been caused to recede along rows into strip sections and the strip sections of adjacent rows being arranged offset with respect to one another. The receding process results in a reduction of an overlap region between two strip sections of adjacent rows in comparison with an overlap region which would be present without the receding process. The second hard mask is removed and the isolation trench structure is filled and planarized with a filling material using the first hard mask subdivided into the strip sections.
摘要翻译：一种制造半导体结构的方法包括：提供半导体衬底，使用第一硬掩模在半导体衬底中提供多个沟槽，并使硬掩模相对于沟槽壁的顶侧相对于沟槽壁后退预定距离用于形成已经退化的第一硬掩模的半导体衬底。使用第二硬掩模在所述半导体衬底中提供隔离沟槽结构，所述隔离沟槽结构将已经被排成一行的所述第一第一硬掩模细分成条形部分，并且相邻行的条带部分相对于另一个。后退过程导致相邻行的两个条状部分之间的重叠区域与不存在后退处理的重叠区域相比会减少。去除第二硬掩模，并且使用被细分为条带部分的第一硬掩模用填充材料填充和平坦化隔离沟槽结构。

5. 发明申请

US20100090264A1 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件的互连结构
公开(公告)号：US20100090264A1
公开(公告)日：2010-04-15
申请号：US12249060
申请日：2008-10-10
申请人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
发明人： Hans-Peter Moll , Gouri Sankar Kar , Martin Popp , Lars Heineck , Peter Lahnor , Arnd Scholz , Stefan Jakschik , Wolfgang Roesner , Gerhard Enders , Werner Graf , Peter Baars , Klaus Muemmler , Bernd Hintze , Andrei Josiek
IPC分类号： H01L27/108 , H01L21/02
CPC分类号： H01L27/10891 , H01L27/10823 , H01L27/10876 , H01L27/10885
摘要： One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.
摘要翻译：一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。互连件包括布置在半导体本体表面下方的金属体。接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。还公开了其它方法，装置和系统。

6. 发明授权

US07605032B2 Method for producing a trench transistor and trench transistor 失效
标题翻译：沟槽晶体管和沟槽晶体管的制造方法
公开(公告)号：US07605032B2
公开(公告)日：2009-10-20
申请号：US11529446
申请日：2006-09-28
申请人： Richard Johannes Luyken , Hans-Peter Moll , Martin Popp , Till Schloesser , Marc Strasser , Rolf Weis
发明人： Richard Johannes Luyken , Hans-Peter Moll , Martin Popp , Till Schloesser , Marc Strasser , Rolf Weis
IPC分类号： H01L21/334 , H01L21/8234 , H01L27/108 , H01L29/94 , H01L21/336 , H01L27/088
CPC分类号： H01L21/26586 , H01L29/66537 , H01L29/66621 , H01L29/7834
摘要： In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.
摘要翻译：在制造沟槽晶体管的方法中，提供第一导电类型的衬底，并且形成衬底中的沟槽和沟槽中的栅极电介质。形成沟槽中作为栅极电介质和第一源极和漏极区域上的栅电极的第一导电填充物。蚀刻后的第一导电填充物是通过将第一导电填料向下蚀刻回到低于第一源的深度并形成漏极区和第二源极和漏极区而产生的。第二源极和漏极区域与第一源极和漏极区域相邻并且延伸至至少与蚀刻后的第一导电填充物一样深的深度。在所述沟槽中形成有在所述蚀刻后的第一导电填充物上方的绝缘间隔物，并且在所述沟槽中设置第二导电填充物作为所述栅电极的上部。

7. 发明申请

US20080044980A1 Method of forming a semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US20080044980A1
公开(公告)日：2008-02-21
申请号：US11507647
申请日：2006-08-21
申请人： Kimberly Wilson , Hans-Peter Moll , Rolf Weis , Phillip Stopford , Frank Ludwig
发明人： Kimberly Wilson , Hans-Peter Moll , Rolf Weis , Phillip Stopford , Frank Ludwig
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , Y10S438/942 , Y10S438/952
摘要： A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5), thereby forming at least a first and a second isolation trench (11a, 11b) extending along the lateral direction (X).
摘要翻译：一种形成半导体器件的方法包括在衬底部分（2）上沉积填充材料（4）和设置在衬底（1）上并具有位于衬底部分上方的开口（10）的介电层（3）（2），去除设置在电介质层（3）上方的填充材料（4），从而在开口（10）内留下介电层（3）的暴露的顶表面（6）和残余填充材料（15）在所述介电层（3）的暴露的顶表面（6）和所述残留填充材料（15）上形成硬掩模材料（5），对所述硬掩模材料（5）进行图案化以形成硬掩模（25），所述硬掩模材料（25）沿着横向方向（X）延伸的沟槽（8a，8b）和暴露邻近电介质层（3）的残余填充材料（15）的部分和与残余填充材料相邻的介电层（3）的部分（15），各向异性地蚀刻介电层（3），残留填充材料（15）和基板（1）选择性地连接到硬掩模（5），从而形成沿着横向（X）延伸的至少第一和第二隔离沟槽（11a，11b）。

8. 发明授权

US07261829B2 Method for masking a recess in a structure having a high aspect ratio 有权
标题翻译：用于掩蔽具有高纵横比的结构中的凹部的方法
公开(公告)号：US07261829B2
公开(公告)日：2007-08-28
申请号：US10501464
申请日：2003-01-08
申请人： Dirk Efferenn , Hans-Peter Moll
发明人： Dirk Efferenn , Hans-Peter Moll
IPC分类号： B44C21/00 , H01L21/00
CPC分类号： H01L21/0337
摘要： A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.
摘要翻译：描述了用于选择性掩蔽的方法。在这种情况下，填充材料被应用于当纵横比高时作为结构的纵横比的函数形成空腔的结构。然后将填充层移除至空腔，并且使用蚀刻工艺，从形成空腔的凹部完全去除填充材料。以这种方式，区域被选择性地暴露。

9. 发明申请

US20050224451A1 Method for masking a recess in a structure with a large aspect ratio 有权
标题翻译：用于掩蔽具有大纵横比的结构中的凹部的方法
公开(公告)号：US20050224451A1
公开(公告)日：2005-10-13
申请号：US10501464
申请日：2003-01-08
申请人： Dirk Efferenn , Hans-Peter Moll
发明人： Dirk Efferenn , Hans-Peter Moll
IPC分类号： H01L21/033 , B44C1/22
CPC分类号： H01L21/0337
摘要： A method for selective masking is described. In this case, a filling material is applied to a structure which, as a function of the aspect ratio of the structure, forms cavities when the aspect ratio is high. The filling layer is then removed as far as the cavities and, using an etching process, filling material is removed completely from the recesses in which the cavities are formed. In this way, areas are exposed selectively.
摘要翻译：描述了用于选择性掩蔽的方法。在这种情况下，填充材料被应用于当纵横比高时作为结构的纵横比的函数形成空腔的结构。然后将填充层移除至空腔，并且使用蚀刻工艺，从形成空腔的凹部完全去除填充材料。以这种方式，区域被选择性地暴露。

10. 发明授权

US06716720B2 Method for filling depressions on a semiconductor wafer 有权
标题翻译：用于在半导体晶片上填充凹陷的方法
公开(公告)号：US06716720B2
公开(公告)日：2004-04-06
申请号：US10378244
申请日：2003-03-03
申请人： Dirk Efferenn , Hans-Peter Moll
发明人： Dirk Efferenn , Hans-Peter Moll
IPC分类号： H01L21762
CPC分类号： H01L21/76224 , H01L21/31056
摘要： A method is disclosed for filling a depression between two vertically adjoining semiconductor layers, in particular an edge depression arising in the context of an isolation trench formation. A covering layer, preferably made of silicon oxide, is deposited in a large-area manner and is then doped with doping material, preferably nitrogen, essentially right over the entire depth of the layer. The doping material provides for an increased rate of removal of the covering layer, so that, after the removal process, the covering layer material only remains in the depressions.
摘要翻译：公开了一种用于填充两个垂直相邻的半导体层之间的凹陷的方法，特别是在隔离沟槽形成的上下文中出现的边缘凹陷。优选由氧化硅制成的覆盖层以大面积方式沉积，然后基本上在层的整个深度上掺杂掺杂材料，优选氮。掺杂材料提供了增加的覆盖层去除率，使得在去除工艺之后，覆盖层材料仅保留在凹陷中。

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