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1. 发明申请

US20070278547A1 MRAM synthetic anitferomagnet structure 有权
标题翻译： MRAM合成非铁磁结构
公开(公告)号：US20070278547A1
公开(公告)日：2007-12-06
申请号：US11444089
申请日：2006-05-31
申请人： Srinivas V. Pietambaram , Bengt J. Akerman , Renu W. Dave , Jason A. Janesky , Nicholas D. Rizzo , Jon M. Slaughter
发明人： Srinivas V. Pietambaram , Bengt J. Akerman , Renu W. Dave , Jason A. Janesky , Nicholas D. Rizzo , Jon M. Slaughter
IPC分类号： H01L29/94
CPC分类号： H01L43/08 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/10
摘要： An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.
摘要翻译： MRAM位（10）包括自由磁区（15），包括反铁磁材料的固定磁区（17）和隧道势垒（16），其包括位于自由磁区（15）和固定磁区（17）。 MRAM位（10）通过使用高H H k（单轴各向异性）的组合，包括表现出明确定义的高电平触发器的固定磁场来避免钉扎层，高饱和场（饱和磁场），理想的软磁特性表现出明确的容易和硬轴。

2. 发明授权

US08497538B2 MRAM synthetic antiferromagnet structure 有权
标题翻译： MRAM合成反铁磁结构
公开(公告)号：US08497538B2
公开(公告)日：2013-07-30
申请号：US11444089
申请日：2006-05-31
申请人： Srinivas V. Pietambaram , Bengt J. Akerman , Renu W. Dave , Jason A. Janesky , Nicholas D. Rizzo , Jon M. Slaughter
发明人： Srinivas V. Pietambaram , Bengt J. Akerman , Renu W. Dave , Jason A. Janesky , Nicholas D. Rizzo , Jon M. Slaughter
IPC分类号： H01L29/94
CPC分类号： H01L43/08 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/10
摘要： An MRAM bit (10) includes a free magnetic region (15), a fixed magnetic region (17) comprising an antiferromagnetic material, and a tunneling barrier (16) comprising a dielectric layer positioned between the free magnetic region (15) and the fixed magnetic region (17). The MRAM bit (10) avoids a pinning layer by comprising a fixed magnetic region exhibiting a well-defined high Hflop using a combination of high Hk (uniaxial anisotropy), high Hsat (saturation field), and ideal soft magnetic properties exhibiting well-defined easy and hard axes.
摘要翻译： MRAM位（10）包括自由磁区（15），包括反铁磁材料的固定磁区（17）和隧道势垒（16），其包括位于自由磁区（15）和固定磁区（17）。 MRAM位（10）通过使用高Hk（单轴各向异性），高Hsat（饱和磁场）和显示明确定义的理想软磁性质的组合，包括表现出明确的高Hflop的固定磁区，避免了钉扎层容易和坚硬的轴。

3. 发明授权

US07683445B2 Enhanced permeability device structures and method 失效
标题翻译：增强渗透性装置结构和方法
公开(公告)号：US07683445B2
公开(公告)日：2010-03-23
申请号：US11740066
申请日：2007-04-25
申请人： Srinivas V. Pietambaram , Nicholas D. Rizzo , Jon M. Slaughter
发明人： Srinivas V. Pietambaram , Nicholas D. Rizzo , Jon M. Slaughter
IPC分类号： H01L29/82
CPC分类号： H01L43/08 , H01L43/12 , Y10S977/838 , Y10S977/933
摘要： Low power magnetoelectronic device structures and methods therefore are provided. The magnetoelectronic device structure (100, 150, 450, 451) comprises a programming line (104, 154, 156, 454, 456), a magnetoelectronic device (102, 152, 452) magnetically coupled to the programming line (104, 154, 156, 454, 456), and an enhanced permeability dielectric (EPD) material (106, 108, 110, 158, 160, 162, 458, 460, 462) disposed adjacent the magnetoelectronic device. The EPD material (106, 108, 110, 158, 160, 162, 458, 460, 462) comprises multiple composite layers (408) of magnetic nano-particles (406) embedded in a dielectric matrix (409). The composition of the composite layers is chosen to provide a predetermined permeability profile. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating the magnetoelectronic device (102, 152, 452) and depositing the programming line (104, 154, 156, 454, 456). The EPD material (106, 108, 110, 158, 160, 162, 458, 460, 462) comprising the multiple composite layers (408) is formed around the magnetoelectronic device (102, 152, 452) and/or between the device (102, 152, 452) and the programming line (104, 154, 156, 454, 456). The presence of the EPD structure (470, 480, 490) in proximity to the programming line (104, 154, 156, 454, 456) and/or the magnetoelectronic device (102, 152, 452) reduces the required programming current.
摘要翻译：因此提供了低功率磁电子器件结构和方法。磁电子器件结构（100,150,450,451）包括编程线（104,154,156,454,456），磁耦合到编程线（104,154,452）的磁电子器件（102,152,452） 156,454,456）以及邻近磁电子器件设置的增强磁导率电介质（EPD）材料（106,108,110,158,160,162,458,460,462）。 EPD材料（106,108,110,158,160,162,458,460,462）包括嵌入电介质矩阵（409）中的磁性纳米颗粒（406）的多个复合层（408）。选择复合层的组成以提供预定的渗透率分布。还提供了一种制造磁电子器件结构的方法。该方法包括制造磁电子器件（102,152,452）并沉积编程线（104,154,156,454,456）。包括多个复合层（408）的EPD材料（106,108,110,158,160,162,458,460,462）形成在磁电子器件（102,152,452）周围和/或在器件（ 102，152,452）和编程线（104,154,156,454,465）。靠近编程线（104,154,156,454,465）和/或磁电子器件（102,152,452）的EPD结构（470,480,490）的存在减少了所需的编程电流。

4. 发明授权

US07285835B2 Low power magnetoelectronic device structures utilizing enhanced permeability materials 有权
标题翻译：利用增强的渗透性材料的低功率磁电子器件结构
公开(公告)号：US07285835B2
公开(公告)日：2007-10-23
申请号：US11066884
申请日：2005-02-24
申请人： Nicholas D. Rizzo , Renu Dave , Jon M. Slaughter , Srinivas V. Pietambaram
发明人： Nicholas D. Rizzo , Renu Dave , Jon M. Slaughter , Srinivas V. Pietambaram
IPC分类号： H01L43/00
CPC分类号： H01L43/08 , H01L43/12 , Y10S977/838 , Y10S977/933
摘要： Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5. A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.
摘要翻译：提供了低功率磁电子器件结构及其制造方法。一个磁电子器件结构（100）包括编程线（104），磁耦合到编程线的磁电子器件（102）和邻近磁电子器件设置的增强的磁导率介电材料（106）。增强的导电介电材料具有不小于约1.5的渗透性。还提供了一种制造磁电子器件结构的方法。该方法包括制造磁电子器件（102）并沉积导线（104）。形成具有不小于约1.5的磁导率的增强磁导率介电材料层（106），其中在制造磁电子器件的步骤和沉积导线的步骤之后，增强磁导率介电材料层位于磁电子器件。

5. 发明授权

US07635902B2 Low power magnetoelectronic device structures utilizing enhanced permeability materials 失效
标题翻译：利用增强的渗透性材料的低功率磁电子器件结构
公开(公告)号：US07635902B2
公开(公告)日：2009-12-22
申请号：US11867189
申请日：2007-10-04
申请人： Nicholas D. Rizzo , Renu Dave , Jon M. Slaughter , Srinivas V. Pietambaram
发明人： Nicholas D. Rizzo , Renu Dave , Jon M. Slaughter , Srinivas V. Pietambaram
IPC分类号： H01L29/82
CPC分类号： H01L43/08 , H01L43/12 , Y10S977/838 , Y10S977/933
摘要： Low power magnetoelectronic device structures and methods for making the same are provided. One magnetoelectronic device structure (100) comprises a programming line (104), a magnetoelectronic device (102) magnetically coupled to the programming line, and an enhanced permeability dielectric material (106) disposed adjacent the magnetoelectronic device. The enhanced permeability dielectric material has a permeability no less than approximately 1.5.A method for making a magnetoelectronic device structure is also provided. The method comprises fabricating a magnetoelectronic device (102) and depositing a conducting line (104). A layer of enhanced permeability dielectric material (106) having a permeability no less than approximately 1.5 is formed, wherein after the step of fabricating a magnetoelectronic device and the step of depositing a conducting line, the layer of enhanced permeability dielectric material is situated adjacent the magnetoelectronic device.
摘要翻译：提供了低功率磁电子器件结构及其制造方法。一个磁电子器件结构（100）包括编程线（104），磁耦合到编程线的磁电子器件（102）和邻近磁电子器件设置的增强的磁导率介电材料（106）。增强的导电介电材料具有不小于约1.5的渗透性。还提供了一种制造磁电子器件结构的方法。该方法包括制造磁电子器件（102）并沉积导线（104）。形成具有不小于约1.5的磁导率的增强磁导率介电材料层（106），其中在制造磁电子器件的步骤和沉积导线的步骤之后，增强磁导率介电材料层位于磁电子器件。

6. 发明授权

US07129098B2 Reduced power magnetoresistive random access memory elements 有权
公开(公告)号：US07129098B2
公开(公告)日：2006-10-31
申请号：US10997118
申请日：2004-11-24
申请人： Nicholas D. Rizzo , Renu W. Dave , Bradley N. Engel , Jason A. Janesky , JiJun Sun
发明人： Nicholas D. Rizzo , Renu W. Dave , Bradley N. Engel , Jason A. Janesky , JiJun Sun
IPC分类号： H01L21/00
CPC分类号： G11C11/16 , H01L27/222 , H01L43/08
摘要： Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin≈(Hsat−Nσsat)−(Hsw+Nσsw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW≅√{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.

7. 发明授权

US07329935B2 Low power magnetoresistive random access memory elements 有权
公开(公告)号：US07329935B2
公开(公告)日：2008-02-12
申请号：US11581951
申请日：2006-10-16
申请人： Nicholas D. Rizzo , Renu W. Dave , Bradley N. Engel , Jason A. Janesky , JiJun Sun
发明人： Nicholas D. Rizzo , Renu W. Dave , Bradley N. Engel , Jason A. Janesky , JiJun Sun
IPC分类号： H01L29/82 , H01L43/00
CPC分类号： G11C11/16 , H01L27/222 , H01L43/08
摘要： Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin≈(Hsat−σsat)−(Hsw+σsw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW≅√{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.

8. 发明授权

US06818961B1 Oblique deposition to induce magnetic anisotropy for MRAM cells 失效
标题翻译：倾斜沉积以诱导MRAM细胞的磁各向异性
公开(公告)号：US06818961B1
公开(公告)日：2004-11-16
申请号：US10611789
申请日：2003-06-30
申请人： Nicholas D. Rizzo , Bradley N. Engel , Jason A. Janesky , Jon M. Slaughter , Jijun Sun
发明人： Nicholas D. Rizzo , Bradley N. Engel , Jason A. Janesky , Jon M. Slaughter , Jijun Sun
IPC分类号： H01L2982
CPC分类号： H01F10/3254 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F10/3272 , H01F41/18 , H01F41/303 , H01L43/12
摘要： A method of fabricating a magnetoresistive tunneling junction cell comprising the steps of providing a substrate with a surface, depositing a first magnetic region (17) having a resultant magnetic moment vector onto the substrate, depositing an electrically insulating material (16) onto the first magnetic region, and depositing a second magnetic region (15) onto the electrically insulating material, wherein at least a portion of one of the first and second magnetic regions is formed by depositing said region at a nonzero deposition angle relative to a direction perpendicular to the surface of the substrate to create an induced anisotropy.
摘要翻译：一种制造磁阻隧道结电池的方法，包括以下步骤：向衬底提供表面;将具有合成磁矩矢量的第一磁区（17）沉积到衬底上，将电绝缘材料（16）沉积到第一磁并且将第二磁性区域（15）沉积到所述电绝缘材料上，其中所述第一和第二磁性区域中的一个的至少一部分相对于垂直于所述表面的方向以非零沉积角沉积所述区域而形成的基底以产生诱导各向异性。

9. 发明申请

US20080096290A1 Magnetic tunnel junction memory and method with etch-stop layer 有权
标题翻译：磁隧道结记忆和具有蚀刻停止层的方法
公开(公告)号：US20080096290A1
公开(公告)日：2008-04-24
申请号：US11584411
申请日：2006-10-19
申请人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
发明人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.
摘要翻译：提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。获得了提高的产量和性能。

10. 发明授权

US07445943B2 Magnetic tunnel junction memory and method with etch-stop layer 有权
标题翻译：磁隧道结记忆和具有蚀刻停止层的方法
公开(公告)号：US07445943B2
公开(公告)日：2008-11-04
申请号：US11584411
申请日：2006-10-19
申请人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
发明人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.
摘要翻译：提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。获得了提高的产量和性能。

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