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1. 发明授权

US06524961B1 Semiconductor device fabricating method 有权
公开(公告)号：US06524961B1
公开(公告)日：2003-02-25
申请号：US09359760
申请日：1999-07-22
申请人： Souichi Katagiri , Kan Yasui , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato , Yoshio Kawamura , Shigeo Moriyama
发明人： Souichi Katagiri , Kan Yasui , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato , Yoshio Kawamura , Shigeo Moriyama
IPC分类号： H01L21461
CPC分类号： B24B37/245 , B24D3/32 , H01L21/31053 , H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.

2. 发明授权

US06723144B2 Semiconductor device fabricating method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US06723144B2
公开(公告)日：2004-04-20
申请号：US10308088
申请日：2002-12-03
申请人： Souichi Katagiri , Kan Yasui , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato , Yoshio Kawamura , Shigeo Moriyama
发明人： Souichi Katagiri , Kan Yasui , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato , Yoshio Kawamura , Shigeo Moriyama
IPC分类号： B24D302
CPC分类号： B24B37/245 , B24D3/32 , H01L21/31053 , H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A film formed on a surface of a wafer on which an integrated circuit is to be constructed can be planarized by using a fixed abrasive tool regardless of the width of elements of a pattern underlying the film. The fixed abrasive tool is liable to form scratches in the surface of the film. A planarizing process of the present invention employs a fixed abrasive tool containing substances harder than the film to be planarized in a content of 10 ppm or below and having a mean pore diameter of 0.2 &mgr;m or below.
摘要翻译：形成在其上将要构造集成电路的晶片的表面上的膜可以通过使用固定的研磨工具进行平面化，而与薄膜下面的图案的元件的宽度无关。固定的研磨工具易于在膜表面形成划痕。本发明的平面化方法使用含有比待平坦化的膜更硬的物质的固定研磨工具，其含量为10ppm以下，平均孔径为0.2μm以下。

3. 发明授权

US06612912B2 Method for fabricating semiconductor device and processing apparatus for processing semiconductor device 失效
标题翻译：半导体装置的制造方法以及半导体装置的处理装置
公开(公告)号：US06612912B2
公开(公告)日：2003-09-02
申请号：US09371003
申请日：1999-08-10
申请人： Kan Yasui , Souichi Katagiri , Shigeo Moriyama , Yoshio Kawamura , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato
发明人： Kan Yasui , Souichi Katagiri , Shigeo Moriyama , Yoshio Kawamura , Ryousei Kawai , Sadayuki Nishimura , Masahiko Sato
IPC分类号： B24B100
CPC分类号： B24B53/017 , B24B1/04 , B24B37/042 , B24B53/12
摘要： A method for fabricating a semiconductor device includes grindstone surface activation treatment by means of a brush or ultrasonic wave carried out when a concave/convex pattern of a semiconductor wafer is planarized by polishing a semiconductor wafer held by a wafer holder by using a grindstone constituted of abrasive grains and material for holding the abrasive grains onto which the semiconductor wafer is pressed with relative motion. The semiconductor wafer is processed with high removal rate and the polishing thickness is controlled accurately.
摘要翻译：一种制造半导体器件的方法包括：当半导体晶片的凹凸图案通过使用由晶片保持器保持的半导体晶片进行平面化而进行的刷子或超声波的磨石表面激活处理，磨料颗粒和用于保持磨料颗粒的材料，半导体晶片被相对运动地压在其上。半导体晶片以高去除率进行处理，并且精确地控制抛光厚度。

4. 发明授权

US06663468B2 Method for polishing surface of semiconductor device substrate 有权
标题翻译：半导体器件基板的研磨方法
公开(公告)号：US06663468B2
公开(公告)日：2003-12-16
申请号：US09754193
申请日：2001-01-05
申请人： Yoshio Kawamura , Kan Yasui , Masahiko Sato , Souichi Katagiri , Masayuki Nagasawa , Kunio Harada , Satoshi Osabe , Ui Yamaguchi
发明人： Yoshio Kawamura , Kan Yasui , Masahiko Sato , Souichi Katagiri , Masayuki Nagasawa , Kunio Harada , Satoshi Osabe , Ui Yamaguchi
IPC分类号： B24B100
CPC分类号： B24B37/32 , H01L21/31053 , H01L21/3212
摘要： The problem of non-uniform polishing properties of a circumferential surface area of a substrate, so-called edge sagging phenomenon, is solved. When a thin film formed on a top surface of the substrate is polished while holding a back surface of the substrate, local stress at a circumferential end of the substrate is reduced by a guide installed so as to surround the substrate. Also, a deformation of the outer circumferential end portion of the substrate is reduced by a recessed groove provided on the guide. Since a thin film formed on the surface can be polished to be flat throughout the surface of the substrate without an occurrence of non-uniform polishing properties of the outer circumferential surface area of the substrate, so-called edge sagging phenomenon, a high-performance semiconductor device can be manufactured at a high yield and low costs.
摘要翻译：解决了基板的圆周表面积的不均匀抛光性能，所谓的边缘下垂现象的问题。当在保持基板的后表面的同时抛光形成在基板的顶表面上的薄膜时，通过安装成围绕基板的引导件来减小基板周向端部的局部应力。此外，通过设置在引导件上的凹槽来减小基板的外周端部的变形。由于形成在表面上的薄膜可以在基板的整个表面上被抛光成平坦的，而不会发生基板的外周表面积的不均匀的抛光性能，所谓的边缘下垂现象，高性能可以以高产率和低成本制造半导体器件。

5. 发明授权

US06589871B2 Processing method, measuring method and producing method of semiconductor devices 失效
标题翻译：半导体器件的加工方法，测量方法和制造方法
公开(公告)号：US06589871B2
公开(公告)日：2003-07-08
申请号：US09941757
申请日：2001-08-30
申请人： Yoshio Kawamura , Souichi Katagiri , Kan Yasui , Masayuki Nagasawa , Ui Yamaguchi
发明人： Yoshio Kawamura , Souichi Katagiri , Kan Yasui , Masayuki Nagasawa , Ui Yamaguchi
IPC分类号： H01L21302
CPC分类号： H01L22/20
摘要： A processing method capable of presenting the processing condition with a high accuracy to improve the productivity, including a step of applying a first processing to a first substrate and a step of applying a second processing to the first substrate or the second processing to a second substrate and determining a correlation function for each of in-plane positions as the data for the difference in a plurality of processing steps to each of the in-plane positions in view of on the in-plain distribution data to the in-plane position of each of the substrate as a result of the plurality of processings, calculating the in-plain distribution characteristics of the substrate under a desired processing condition in view of the correlation function and processing the substrate based on the in-plain distribution characteristics.
摘要翻译：一种处理方法，其能够高精度地呈现处理条件以提高生产率，包括对第一基板施加第一处理的步骤和对第一基板施加第二处理的步骤或第二处理的步骤以及将每个平面内位置的相关函数确定为多个处理步骤中的差数据的数据，以便在每个平面内位置中考虑到不均匀分布数据到每个平面内位置的平面内位置作为多个处理的结果，考虑到相关函数，在所需的处理条件下计算衬底的不均匀分布特性，并且基于平原分布特性来处理衬底。

6. 发明授权

US06777337B2 Planarizing method of semiconductor wafer and apparatus thereof 失效
标题翻译：半导体晶片的平面化方法及其装置
公开(公告)号：US06777337B2
公开(公告)日：2004-08-17
申请号：US09910904
申请日：2001-07-24
申请人： Kan Yasui , Souichi Katagiri , Masayuki Nagasawa , Ui Yamaguchi , Yoshio Kawamura
发明人： Kan Yasui , Souichi Katagiri , Masayuki Nagasawa , Ui Yamaguchi , Yoshio Kawamura
IPC分类号： H01L21302
CPC分类号： B24B37/042 , H01L21/31053
摘要： In a production process of a semiconductor device, planarizing of a wafer surface pattern can be performed to attain high planarity, good uniformity in the removal amount and improved controllability. This process include a step of planarizing a semiconductor wafer, from which at least two different films have been exposed, by polishing with a grindstone and a dispersant-containing processing liquid.
摘要翻译：在半导体装置的制造方法中，可以进行晶片表面图案的平坦化，以获得高的平坦度，良好的去除量均匀性和改进的可控性。该方法包括通过用磨石和含分散剂处理液进行抛光来平坦化半导体晶片的步骤，从半导体晶片至少暴露出两个不同的膜。

7. 发明授权

US06734103B2 Method of polishing a semiconductor device 失效
标题翻译：抛光半导体器件的方法
公开(公告)号：US06734103B2
公开(公告)日：2004-05-11
申请号：US10081212
申请日：2002-02-25
申请人： Souichi Katagiri , Ui Yamaguchi , Seiichi Kondo , Kan Yasui , Yoshio Kawamura
发明人： Souichi Katagiri , Ui Yamaguchi , Seiichi Kondo , Kan Yasui , Yoshio Kawamura
IPC分类号： H01L21302
CPC分类号： B24B7/228 , B24B53/02 , C23F3/00 , H01L21/3212 , H01L21/7684
摘要： A method of manufacturing is described wherein a semiconductor device has a substrate as workpiece with an insulation film formed on the substrate, openings formed inside the insulation film, a first conductive film is formed inside the openings and on a surface of the insulation film, a second conductive film is formed on the first conductive film, and the first and the second conductive films are formed inside openings by planarizing a surface of second conductive film and a surface part of the first conductive film with a fixed abrasive tool. The method includes supplying a first processing liquid, planarizing the surface of the second conductive film with the first processing liquid and the fixed abrasive tool, switching the supply of liquid from a first processing liquid to a second processing liquid, and planarizing the surface of second conductive film and the surface of part of the first conductive film with the second processing liquid and the fixed abrasive tool.
摘要翻译：描述了一种制造方法，其中半导体器件具有作为工件的基板，在基板上形成绝缘膜，形成在绝缘膜内部的开口，第一导电膜形成在开口内部和绝缘膜的表面上，第二导电膜形成在第一导电膜上，并且通过用固定的研磨工具平面化第二导电膜的表面和第一导电膜的表面部分，在开口内形成第一和第二导电膜。该方法包括提供第一处理液体，将第二导电膜的表面与第一处理液体和固定研磨工具平坦化，将液体从第一处理液体切换到第二处理液体，并将第二处理液体的表面平坦化导电膜和第一导电膜的部分表面与第二处理液和固定研磨工具。

8. 发明授权

US06565424B2 Method and apparatus for planarizing semiconductor device 失效
公开(公告)号：US06565424B2
公开(公告)日：2003-05-20
申请号：US09863264
申请日：2001-05-24
申请人： Souichi Katagiri , Yoshio Kawamura , Kan Yasui , Masayuki Nagasawa , Ui Yamaguchi
发明人： Souichi Katagiri , Yoshio Kawamura , Kan Yasui , Masayuki Nagasawa , Ui Yamaguchi
IPC分类号： B24B100
CPC分类号： B24B37/30 , B24B37/042 , B24B37/32
摘要： The invention provides a process apparatus including a wafer holder, and a process method, in which high planarization performance, scratch free process, narrow edge exclusion and high uniformity can be maintained for more than 10,000 processed wafers. The invention is achieved by providing a unit for keeping a retainer and surface of a polishing wheel non-contact with each other and controlling the gap within a certain range and by setting compression strength of the retainer at more than 3,000 kg/cm2.

9. 发明授权

US07166013B2 Polishing apparatus and method for producing semiconductors using the apparatus 有权
标题翻译：抛光装置及其制造方法
公开(公告)号：US07166013B2
公开(公告)日：2007-01-23
申请号：US11004991
申请日：2004-12-07
申请人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
发明人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
IPC分类号： B24B49/00 , B24B51/00 , B24B1/00 , B24B29/00
CPC分类号： B24B53/017 , B24B37/042 , B24B41/04 , B24B53/12
摘要： The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended.Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate.The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.
摘要翻译：本发明涉及一种抛光装置以及使用该装置的半导体制造方法。磨石表面的磨合通过施胶处理进行研磨，由此可以进行工具表面的修整，同时防止在磨石表面产生裂纹，这是产生划痕的原因。此外，可以保证修整工具的表面的平整度，因为切割的尺寸大小; 即使使用了几厘米厚的砂轮，也可以保持平坦度，并且可以总是执行具有较少的面内不均匀性的处理。因此，修整工具的寿命可以大大延长。此外，与晶片的处理联合进行本施胶修整，从而能够提高装置的生产量以及维持处理速度。本装置和方法对于具有不规则性的各种衬底表面的平坦化是有效的。

10. 发明申请

US20060057940A1 Polishing apparatus and method for producing semiconductors using the apparatus 有权
公开(公告)号：US20060057940A1
公开(公告)日：2006-03-16
申请号：US11267306
申请日：2005-11-07
申请人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
发明人： Shigeo Moriyama , Yoshihiro Ishida , Takashi Kugaya , Shigeo Ootsuki , Soichi Katagiri , Sadayuki Nishimura , Ryosei Kawai , Kan Yasui
IPC分类号： B24B51/00 , B24B7/30 , B24B1/00 , B24B29/00 , B24B21/18
CPC分类号： B24B53/017 , B24B37/042 , B24B41/04 , B24B53/02 , B24B53/12
摘要： The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended. Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate. The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.

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