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1. 发明专利

JP2011135456A Receiver, receiving method, program and receiving system 审中-公开
标题翻译：接收器，接收方法，程序和接收系统
公开(公告)号：JP2011135456A
公开(公告)日：2011-07-07
申请号：JP2009294545
申请日：2009-12-25
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , SHINTANI OSAMU , SAKAI HITOSHI
IPC分类号： H04J11/00
CPC分类号： H04L5/0007 , H04L1/0052 , H04L1/0071
摘要： PROBLEM TO BE SOLVED: To reduce circuit scale.
SOLUTION: When the output of one time deinterleaver 33A is performed, a Data PLP (physical layer pipe) of another time deinterleaver 33B is NTI>1 and writing of a leading TI-block among NTI pieces of TI-blocks into a memory 52 is completed, a control section 51 switches the output to the time deinterleaver 33B and performs preferential output, until the output of NTI-1 or NTI pieces of TI-blocks among the NTI pieces of TI-blocks are completed. Then, when the output of the NTI-1 or NTI pieces of TI-blocks are completed, the control section 51 performs switching from the preferentially outputting time deinterleaver 33B to the time deinterleaver 33A which is interrupted in the middle and resumes output. Thus, missing of data is prevented and an error-correcting section 23 can be shared. The present invention is applicable to receivers which receive signal by an M-PLP system in DVB-T2.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：减少电路规模。解决方案：当执行一次解交织器33A的输出时，另一个时间解交织器33B的Data PLP（物理层管道）为NTI> 1，并且将NTI个TI块中的前导TI块写入到存储器52完成，控制部分51将输出切换到时间解交织器33B并执行优先输出，直到完成了NTI个TI块中的NTI-1或NTI个TI块的输出。然后，当NTI-1或NTI个TI块的输出完成时，控制部分51执行从优先输出时间解交织器33B到在中间中断的时间解交织器33A的切换并恢复输出。因此，防止数据丢失，并且可以共享错误校正部分23。本发明适用于DVB-T2中由M-PLP系统接收信号的接收机。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2010226474A Receiving apparatus and method, program, and receiving system 有权
标题翻译：接收装置和方法，程序和接收系统
公开(公告)号：JP2010226474A
公开(公告)日：2010-10-07
申请号：JP2009072161
申请日：2009-03-24
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , SHINTANI OSAMU
IPC分类号： H04L1/00 , H03M13/19
CPC分类号： H03M13/1105 , H03M13/15 , H03M13/152 , H03M13/27 , H03M13/2906 , H03M13/6552 , H04L1/0057 , H04L1/0065 , H04L1/0071 , H04L2001/0093
摘要： PROBLEM TO BE SOLVED: To decode PLP and L1 by one LDPC decoder in a DVB-T.2 receiver.
SOLUTION: In a receiving apparatus, a timing chart is indicated in symbol units for each of an input signal Sa of a demodulator, an output signal Sb of the demodulator, an output signal Sc of a frequency deinterleaver, and an output signal Sd (a target of LDPC decoding) of an LDPC decoder. Among the output signals Sc of the frequency deinterleaver, PLP (data) is supplied to a time deinterleaver, while L1 (included in a P2 symbol) is supplied to the LDPC decoder. As a result, a decoding target of the LDPC decoder becomes the signal Sd as shown in Fig.2. That is, when data symbols are accumulated in the time deinterleaver, LDPC decoding for an LDPC code of the corresponding PLP (data) is started. In addition, when L1 is output from the frequency deinterleaver, LDPC decoding for the L1 is interrupted. The receiving apparatus can be applied to the receiving apparatus of DVB-T.2.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过DVB-T.2接收机中的一个LDPC解码器对PLP和L1进行解码。解决方案：在接收装置中，对于解调器的输入信号Sa，解调器的输出信号Sb，频率解交织器的输出信号Sc和输出信号，以符号单位指示时序图 Sd（LDPC解码的目标）。在频率解交织器的输出信号Sc中，PLP（数据）被提供给时间去交织器，而L1（包括在P2符号中）被提供给LDPC解码器。结果，如图2所示，LDPC解码器的解码对象成为信号Sd。也就是说，当在时间去交织器中累积数据符号时，开始对应于PLP（数据）的LDPC码的LDPC解码。此外，当L1从频率去交织器输出时，L1的LDPC解码被中断。接收装置可以应用于DVB-T.2的接收装置。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2006304129A Decoding apparatus and decoding method 有权
标题翻译：解码设备和解码方法
公开(公告)号：JP2006304129A
公开(公告)日：2006-11-02
申请号：JP2005125962
申请日：2005-04-25
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , MIYAUCHI TOSHIYUKI , SHINTANI OSAMU
IPC分类号： H03M13/19
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： PROBLEM TO BE SOLVED: To provide a decoding apparatus capable of highly accurately decoding LDPC codes while suppressing an increase in the size of the apparatus. SOLUTION: A calculation section 1102 uses a decoding halfway result D1101 supplied from a decoding halfway result storage memory 1104 via a cyclic shift circuit 1101 to carry out a first arithmetic operation corresponding to three check node arithmetic operations and stores a decoding halfway result D1102 obtained as a result into a decoding halfway result storage memory 1103. A calculation section 415 uses a decoding halfway result D414 supplied from the decoding halfway result storage memory 1103 via the cyclic shift circuit to carry out a second arithmetic operation corresponding to arithmetic operations of six variable nodes and stores a decoding halfway result D415 obtained as a result into a decoding halfway result storage memory 1104. The decoding apparatus can be applied to, e.g. tuners for receiving satellite broadcasting. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决的问题：提供一种能够高精度地解码LDPC码的解码装置，同时抑制装置尺寸的增加。解决方案：计算部分1102使用经由循环移位电路1101从解码中途结果存储存储器1104提供的解码中途结果D1101来执行与三个校验节点算术运算相对应的第一运算，并存储解码中途结果 D1102作为结果被获得到解码中途结果存储存储器1103中。计算部分415使用经由循环移位电路从解码中途结果存储存储器1103提供的解码中途结果D414，执行与算术运算对应的第二算术运算六个可变节点，并将作为结果获得的解码中途结果D415存储到解码中途结果存储存储器1104中。解码装置可以应用于，例如用于接收卫星广播的调谐器。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2012114527A Data processing apparatus and data processing method 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：JP2012114527A
公开(公告)日：2012-06-14
申请号：JP2010259665
申请日：2010-11-22
申请人： Sony Corp , ソニー株式会社
发明人： SHINTANI OSAMU , YOKOGAWA MINESHI , LACHLAN BRUCE MICHAEL
IPC分类号： H03M13/29 , H04L1/00
CPC分类号： H04L1/004 , H03M13/1102 , H03M13/152 , H03M13/253 , H03M13/255 , H03M13/618 , H03M13/6362 , H03M13/6552 , H04L1/0043 , H04L1/0052 , H04L1/0057 , H04L1/0065 , H04L1/0068 , H04L1/0072
摘要： PROBLEM TO BE SOLVED: To facilitate processing of control data with an improved PAPR.SOLUTION: In a transmission apparatus, a padder 21 pads control data necessary for demodulation with dummy data of zero, and a scrambler 101 scrambles the control data with the padding (padded control data). A replacement section 121 replaces the scrambled dummy data in the scrambled, padded control data with the dummy data, and a BCH encoder 22 and an LDPC encoder 23 apply BCH coding and LDPC coding as error correction coding to the replacement data resulting from the replacement. A shortening section 24 applies shortening, including deletion of the dummy data included in the LDPC code and puncturing of parity bits of the LDPC code. The present invention is applicable, for example, to the transmission of error-correction-coded control data.
摘要翻译：要解决的问题：为了便于利用改进的PAPR处理控制数据。解决方案：在发送装置中，填充器21用零的伪数据填充解调所需的控制数据，并且加扰器101用填充（填充的控制数据）对控制数据进行加扰。替换部分121用伪数据替换经加扰的填充的控制数据中的加密伪数据，并且BCH编码器22和LDPC编码器23将BCH编码和LDPC编码作为纠错编码应用于由替换产生的替换数据。缩短部分24应用缩短，包括删除包括在LDPC码中的伪数据和对LDPC码的奇偶校验位的删余。本发明可以应用于例如错误校正编码控制数据的发送。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2009010767A Encoder and decoder, and transmission apparatus and reception apparatus 有权
标题翻译：编码器和解码器，以及传输装置和接收装置
公开(公告)号：JP2009010767A
公开(公告)日：2009-01-15
申请号：JP2007171094
申请日：2007-06-28
申请人： Nippon Hoso Kyokai , Sony Corp , ソニー株式会社 , 日本放送協会
发明人： YOKOGAWA MINESHI , YAMAMOTO MAKIKO , SHINTANI OSAMU , NAKANE MISA , OKADA SATOSHI , HASHIMOTO AKINORI , SUZUKI YOICHI , SHIYOUGEN KAZUYOSHI , TANAKA YOSHIJI , SUJIKAI HISASHI , KIMURA TAKESHI , KOJIMA MASAAKI
IPC分类号： H03M13/19
CPC分类号： H03M13/1185 , H03M13/1102 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2906 , H03M13/6356
摘要： PROBLEM TO BE SOLVED: To provide an encoder and decoder for performing LDPC (low density parity check) encoding/decoding optimal for a slot structure, and a transmission apparatus and a reception apparatus, in a transmission system for multiplexing, in a time division manner, a plurality of kinds of digital modulation systems. SOLUTION: Encoders 11-1, 11-2 perform LDPC encoding on predetermined data using a specific check matrix. The specific check matrix is generated by disposing one element of a partial matrix corresponding to an information length N-P corresponding to an encoding rate in a cycle for the unit of 374 columns in a column direction with a predetermined check matrix initial value table as an initial value. The check matrix initial value table is predetermined for each encoding rate of 11/40, 41/120, 49/120, 61/120, 73/120, 27/40, 89/120, 97/120, 101/120, 7/8, 109/120 with the identical code length N. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种编码器和解码器，用于在用于多路复用的传输系统中执行针对时隙结构的LDPC（低密度奇偶校验）编码/解码以及发送装置和接收装置，在时分方式，多种数字调制系统。解决方案：编码器11-1,11-2使用特定的校验矩阵对预定数据执行LDPC编码。特定的校验矩阵是通过将预定的校验矩阵初始值表作为初始值的列方向的374列的单位的循环中的与编码率相对应的信息长度NP对应的部分矩阵的一个元素。校验矩阵初始值表对于11 / 40,41 / 120,49 / 120,61 / 120,73 / 120,27 / 40,89 / 120,97 / 120,101 / 120,7的每个编码率是预先确定的 / 8,109/120，代码长度N相同。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2006304130A Decoding apparatus and decoding method 有权
标题翻译：解码设备和解码方法
公开(公告)号：JP2006304130A
公开(公告)日：2006-11-02
申请号：JP2005125963
申请日：2005-04-25
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , SHINOHARA YUJI , SHINTANI OSAMU
IPC分类号： H03M13/19
CPC分类号： H03M13/1111 , H03M13/1131 , H03M13/1134 , H03M13/1137 , H03M13/118 , H03M13/6577
摘要： PROBLEM TO BE SOLVED: To highly accurately decode LDPC codes while suppressing an increase in the size of the apparatus. SOLUTION: A check node calculator 171 carries out a check node arithmetic operation for decoding LDPC codes and including arithmetic operations of a nonlinear function ϕ(x) and an inverse function ϕ -1 (x) of the nonlinear function. A variable node calculator 103 carries out a variable node arithmetic operation of variable nodes for decoding the LDPC codes. Then the check node calculator 171 and the variable node calculator 103 use a second quantization value representing a numeral with higher accuracy than that of a first quantization value up to processes of the arithmetic operation of the inverse function ϕ -1 (x) after the arithmetic operation of the nonlinear function ϕ(x) among the processes carried out by the check node arithmetic operation and the variable node arithmetic operation, and use the first quantization value for the other processes. The decoding apparatus can be applied to, e.g. tuners for receiving satellite broadcasting. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在抑制设备尺寸增加的同时高精度地解码LDPC码。解决方案：校验节点计算器171执行用于解码LDPC码的校验节点算术运算，并且包括非线性函数φ（x）和逆函数φ -1 （x）的算术运算，的非线性函数。可变节点计算器103对可变节点执行用于解码LDPC码的可变节点算术运算。然后，校验节点计算器171和可变节点计算器103使用表示与第一量化值相比具有更高精度的数字的第二量化值，直到逆函数φ -1

7. 发明专利

JP2011135457A Reception apparatus and method, program, and reception system 有权
标题翻译：接收装置和方法，程序和接收系统
公开(公告)号：JP2011135457A
公开(公告)日：2011-07-07
申请号：JP2009294546
申请日：2009-12-25
申请人： Sony Corp , ソニー株式会社
发明人： SHINTANI OSAMU , HORIGUCHI TAKASHI
IPC分类号： H04J11/00 , H04B1/16
CPC分类号： H04L27/2647
摘要： PROBLEM TO BE SOLVED: To accelerate decoding processing by promptly performing PLP (Physical Layer Pipe) search processing.
SOLUTION: In a reception apparatus, a control circuit 31 causes a register 33 to store a PLP information signal of a Common PLP until one T2 frame ends, and determines whether or not a Group ID contained in the PLP information signal is matched with a specific Group ID contained in a PLP information signal of a designated Data PLP. If these Group IDs are matched, the stored PLP information signal is supplied to a decoding processing section 13. Thus, since PLP search processing is concluded within one T2 frame, PLP search processing can be promptly performed, thereby accelerating decoding processing with the decoding processing section 13. This invention therefore can be applied to a reception apparatus which receives a signal according to an M-PLP system in DVB-T2.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过及时执行PLP（物理层管道）搜索处理来加速解码处理。解决方案：在接收装置中，控制电路31使寄存器33存储公共PLP的PLP信息信号，直到一个T2帧结束，并确定PLP信息信号中包含的组ID是否匹配具有包含在指定数据PLP的PLP信息信号中的特定组ID。如果这些组ID匹配，则存储的PLP信息信号被提供给解码处理部分13.因此，由于PLP搜索处理在一个T2帧内结束，因此可以迅速执行PLP搜索处理，从而通过解码处理来加速解码处理因此，本发明可以应用于在DVB-T2中接收根据M-PLP系统的信号的接收装置。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2009027302A Decoder and decoding method 有权
标题翻译：解码和解码方法
公开(公告)号：JP2009027302A
公开(公告)日：2009-02-05
申请号：JP2007186565
申请日：2007-07-18
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , SHINTANI OSAMU
IPC分类号： H03M13/19
摘要： PROBLEM TO BE SOLVED: To reduce a circuit scale without deteriorating decoding performance in decoding a LDPC (Low Density Parity Check) code. SOLUTION: An input buffer 513 temporarily stores reception values of intermittently input LDPC codes and continuously reads the stored reception values. A reception value memory 601 of a connection memory 514 stores the reception values continuously read by the input buffer 513 and reads every P stored reception values. A calculating part decodes every P reception values which are read for P reception values by the reception value memory 601. A message memory 602 of the connection memory 514 stores messages being halfway results of decoding, reads every P stored messages and outputs them to the calculating part. Further, the bit width of the input buffer 513 is smaller than the bit width of the connection memory 514. This invention is applicable, for example, to a tuner for receiving satellite broadcasting. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：在解码LDPC（低密度奇偶校验）码的同时降低电路规模而不降低解码性能。解决方案：输入缓冲器513临时存储间歇输入的LDPC码的接收值，并连续读取存储的接收值。连接存储器514的接收值存储器601存储由输入缓冲器513连续读取的接收值，并读取每个P个存储的接收值。计算部分对由接收值存储器601读取的P个接收值的每个P个接收值进行解码。连接存储器514的消息存储器602存储作为解码结果的一半的消息，读取每个P个存储的消息，并将它们输出到计算部分。此外，输入缓冲器513的位宽小于连接存储器514的位宽度。本发明可以应用于例如用于接收卫星广播的调谐器。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2011097245A Receiving apparatus, receiving method program and receiving system 审中-公开
标题翻译：接收装置，接收方法程序和接收系统
公开(公告)号：JP2011097245A
公开(公告)日：2011-05-12
申请号：JP2009247757
申请日：2009-10-28
申请人： Sony Corp , ソニー株式会社
发明人： SHINTANI OSAMU , YOKOGAWA MINESHI , YOSHIMOCHI NAOKI
IPC分类号： H03M13/29 , H03M13/19 , H04L1/00
CPC分类号： H04L1/005 , H03M13/1102 , H03M13/152 , H03M13/2906 , H03M13/6552 , H04L1/0057
摘要： PROBLEM TO BE SOLVED: To prevent missing of data, when frame data in which an inner code and an outer code are used as error correction codes are decoded. SOLUTION: In an LDPC-decoding part 11, LDPC decoding processing is performed on each code frame, and the data of a decoding result are sequentially output to an LDPC output buffer 12. In a BCH-decoding part 13, BCH-decoding processing of the data output from the LDPC output buffer 12 is performed. When the output of the data of an LDPC decoding result is started from the LDPC decoding part 11, the data of the LDPC-decoding result is stored, by giving priority over the output of the data from the LDPC output buffer 12 to the ECH-decoding part 13. When storage of the data of the LDPC-decoding result is finished, the suspended output of the data is resumed. The present invention is applicable to receiving apparatuses that follows the provisions of DVB-T2. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了防止丢失数据，将内部码和外部码用作纠错码的帧数据进行解码。解码方案：在LDPC解码部分11中，对每个码帧执行LDPC解码处理，并将解码结果的数据顺序地输出到LDPC输出缓冲器12.在BCH解码部分13中，BCH- 执行从LDPC输出缓冲器12输出的数据的解码处理。当从LDPC解码部分11开始LDPC解码结果的数据的输出时，通过将数据从LDPC输出缓冲器12输出到ECH- 解码部分13.当LDPC解码结果的数据的存储结束时，数据的暂停输出被恢复。本发明适用于遵循DVB-T2规定的接收装置。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2008278191A Decoding device and decoding method 有权
标题翻译：解码设备和解码方法
公开(公告)号：JP2008278191A
公开(公告)日：2008-11-13
申请号：JP2007119097
申请日：2007-04-27
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , HIRAYAMA YUICHI , SHINTANI OSAMU , OKADA SATOSHI
IPC分类号： H03M13/19
摘要： PROBLEM TO BE SOLVED: To decrease a circuit scale when LDPC codes are decoded. SOLUTION: An input buffer 513 temporarily stores received values of LDPC codes which are intermittently input, and successively reads out the stored received values. A memory 514 for received value storage stores the received values successively read out of the input buffer 513 and reads every six stored received values. A calculator decodes every six received values which are read out of the memory 514 for received value storage by six at each time. The bit width of the input buffer 513 is smaller than the bit width of the memory 514 for received value storage. The present invention is applicable to, for example, a tuner which receives a satellite broadcast. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了在LDPC码被解码时减小电路规模。解决方案：输入缓冲器513临时存储间歇输入的LDPC码的接收值，并连续地读出所存储的接收值。用于接收值存储的存储器514存储从输入缓冲器513连续读出的接收值，并读取每六个存储的接收值。计算器将每六个接收到的值接收到存储器514中，以便每次接收值存储6次。输入缓冲器513的位宽小于用于接收值存储的存储器514的位宽。本发明可应用于例如接收卫星广播的调谐器。版权所有（C）2009，JPO＆INPIT

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