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1. 发明专利

JP2009010767A Encoder and decoder, and transmission apparatus and reception apparatus 有权
标题翻译：编码器和解码器，以及传输装置和接收装置
公开(公告)号：JP2009010767A
公开(公告)日：2009-01-15
申请号：JP2007171094
申请日：2007-06-28
申请人： Nippon Hoso Kyokai , Sony Corp , ソニー株式会社 , 日本放送協会
发明人： YOKOGAWA MINESHI , YAMAMOTO MAKIKO , SHINTANI OSAMU , NAKANE MISA , OKADA SATOSHI , HASHIMOTO AKINORI , SUZUKI YOICHI , SHIYOUGEN KAZUYOSHI , TANAKA YOSHIJI , SUJIKAI HISASHI , KIMURA TAKESHI , KOJIMA MASAAKI
IPC分类号： H03M13/19
CPC分类号： H03M13/1185 , H03M13/1102 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2906 , H03M13/6356
摘要： PROBLEM TO BE SOLVED: To provide an encoder and decoder for performing LDPC (low density parity check) encoding/decoding optimal for a slot structure, and a transmission apparatus and a reception apparatus, in a transmission system for multiplexing, in a time division manner, a plurality of kinds of digital modulation systems. SOLUTION: Encoders 11-1, 11-2 perform LDPC encoding on predetermined data using a specific check matrix. The specific check matrix is generated by disposing one element of a partial matrix corresponding to an information length N-P corresponding to an encoding rate in a cycle for the unit of 374 columns in a column direction with a predetermined check matrix initial value table as an initial value. The check matrix initial value table is predetermined for each encoding rate of 11/40, 41/120, 49/120, 61/120, 73/120, 27/40, 89/120, 97/120, 101/120, 7/8, 109/120 with the identical code length N. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种编码器和解码器，用于在用于多路复用的传输系统中执行针对时隙结构的LDPC（低密度奇偶校验）编码/解码以及发送装置和接收装置，在时分方式，多种数字调制系统。解决方案：编码器11-1,11-2使用特定的校验矩阵对预定数据执行LDPC编码。特定的校验矩阵是通过将预定的校验矩阵初始值表作为初始值的列方向的374列的单位的循环中的与编码率相对应的信息长度NP对应的部分矩阵的一个元素。校验矩阵初始值表对于11 / 40,41 / 120,49 / 120,61 / 120,73 / 120,27 / 40,89 / 120,97 / 120,101 / 120,7的每个编码率是预先确定的 / 8,109/120，代码长度N相同。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2007036776A Decoding apparatus and decoding method 审中-公开
标题翻译：解码设备和解码方法
公开(公告)号：JP2007036776A
公开(公告)日：2007-02-08
申请号：JP2005218331
申请日：2005-07-28
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , NAKANE MISA
IPC分类号： H03M13/19 , G06F11/10
摘要： PROBLEM TO BE SOLVED: To improve the throughput of a decoding apparatus. SOLUTION: A receiving part 811 simultaneously stores two receiving data D416 in each operation and simultaneously supplies six already stored receiving data D811 to a calculation part 415 in each operation. The calculation part 415 executes second operation, by using the receiving data D811 and a decoding halfway result D414, obtained as a result of first operation and a calculation part 412 executes the first operation by using a decoding halfway result D411, obtained as a result of the second operation and a decoding halfway result D413, obtained as a result of the preceding first operation. A decoding halfway result D415, obtained as a result of the final second operation is supplied to an output part 812, which stores the decoding halfway result D415. The output part 812 simultaneously reads out two already stored halfway results D415 as decoded results in each operation and outputs the read decoded results. This invention can be applied to tuners that receive satellite broadcasting, for instance. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决方案的问题：提高解码装置的吞吐量。解决方案：接收部分811在每个操作中同时存储两个接收数据D416，并且在每个操作中同时将六个已存储的接收数据D811提供给计算部分415。计算部415通过使用作为第一操作的结果而获得的接收数据D811和解码中途结果D4141执行第二操作，并且计算部412通过使用作为结果的结果获得的解码中途结果D411执行第一操作作为前述第一操作的结果获得的第二操作和解码中途结果D413。作为最后的第二操作的结果获得的解码中途结果D415被提供给存储解码中途结果D415的输出部分812。输出部812在每个操作中同时读出两个已经存储的中途结果D415作为解码结果，并输出读取的解码结果。例如，本发明可以应用于接收卫星广播的调谐器。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2013162220A Demodulation device, demodulation method, and program 有权
标题翻译：解调设备，解调方法和程序
公开(公告)号：JP2013162220A
公开(公告)日：2013-08-19
申请号：JP2012020868
申请日：2012-02-02
申请人： Sony Corp , ソニー株式会社
发明人： KAMATA HIROYUKI , HIRAYAMA YUICHI , NAKANE MISA
IPC分类号： H04L27/22 , H04L27/38
CPC分类号： H03D3/007 , H03D2200/005 , H04L1/0047 , H04L27/22 , H04L27/38 , H04L2027/0065
摘要： PROBLEM TO BE SOLVED: To realize demodulation processing, even when an I channel signal and a Q channel signal are reversed when they are input, at speed comparable to the case in which no reversal has occurred.SOLUTION: A frequency correction unit 31 establishes synchronization of the frequency and the clock on the basis of a signal of a frequency synchronization unit 32. A channel reversal detection unit 35 of a frame synchronization unit 37 detects whether there has been a reversal of the I channel signal and the Q channel signal, and supplies, as the detection result, a channel reversal detection result to the channel reversal control unit 35. The channel reversal control unit 35 swaps the I channel signal and the Q channel signal if, on the basis of the channel reversal detection result, a reversal has occurred. This technique can be applied to demodulation devices.
摘要翻译：要解决的问题：即使当I信道信号和Q信道信号被输入时，即使在与没有发生反转的情况相当的速度下，也可以实现解调处理。解决方案：频率校正单元31建立同步基于频率同步单元32的信号的频率和时钟。帧同步单元37的信道反转检测单元35检测是否存在I信道信号和Q信道信号的反转，以及将通道反转检测结果作为检测结果提供给信道反转控制单元35.信道反转控制单元35根据信道反转检测结果反转I交换I信道信号和Q信道信号已经发生了。这种技术可以应用于解调设备。

4. 发明专利

JP2006304132A Coding apparatus and coding method 有权
标题翻译：编码设备和编码方法
公开(公告)号：JP2006304132A
公开(公告)日：2006-11-02
申请号：JP2005125965
申请日：2005-04-25
申请人： Sony Corp , ソニー株式会社
发明人： YOKOGAWA MINESHI , YAMAMOTO MAKIKO , NAKANE MISA
IPC分类号： H03M13/19
CPC分类号： H03M13/1168 , H03M13/1137 , H03M13/116 , H03M13/1185 , H03M13/6502 , H03M13/6516 , H03M13/6561
摘要： PROBLEM TO BE SOLVED: To provide a coding apparatus the circuit scale of which is reduced without changing an operating speed of coding of linear codes. SOLUTION: An adder 13 summates a product between a 6-bit information word D12 supplied from a cyclic shift circuit 12 and an information part of a check matrix H corresponding to the information of the information word in the unit of 6 rows by the rows and gives the result to a RAM 14 as a sum D15. The RAM 14 stores the sum D15. Further, the RAM 14 reads the 2-bit sum D15 having been already stored and gives the sum D15 to an accumulator 16 as a sum D17 via an interleaver 15. The accumulator 16 summates the sum D17 and outputs a parity pit D18 obtained as a result as a parity bit p of a code word c via a selector 17. The coding apparatus can be applied to apparatuses of broadcast stations for transmitting satellite broadcasting. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种编码装置，其电路规模在不改变线性编码编码的操作速度的情况下被减少。解决方案：加法器13将从循环移位电路12提供的6位信息字D12与以6行为单位的信息字的信息相对应的校验矩阵H的信息部分之间的乘积相加，行并将结果提供给RAM14作为总和D15。 RAM14存储总和D15。此外，RAM14读取已经存储的2位和D15，并且经由交织器15将和D15给予累加器16作为和D17。累加器16对和D17进行求和，并输出获得的奇偶校验位D18 通过选择器17作为码字c的奇偶校验位p。编码装置可以应用于用于发送卫星广播的广播站的装置。版权所有（C）2007，JPO＆INPIT

5. 发明专利

BRPI0823264A2 未知
公开(公告)号：BRPI0823264A2
公开(公告)日：2013-09-24
申请号：BRPI0823264
申请日：2008-06-25
申请人： SONY CORP , JAPAN BROADCASTING CORP
发明人： YOKOKAWA TAKASHI , YAMAMOTO MAKIKO , SHINYA OSAMU , NAKANE MISA , OKADA SATOSHI , SUZUKI YOICHI , HASHIMOTO AKINORI , SHOGEN KAZUYOSHI , SUJIKAI HISASHI , KIMURA TAKESHI , KOJIMA MASAAKI , TANAKA SHOJI
IPC分类号： H03M13/19

6. 发明专利

BRPI0813643A2 未知
公开(公告)号：BRPI0813643A2
公开(公告)日：2011-09-13
申请号：BRPI0813643
申请日：2008-06-25
申请人： SONY CORP , JAPAN BROADCASTING CORP
发明人： YOKOKAWA TAKASHI , YAMAMOTO MAKIKO , SHINYA OSAMU , NAKANE MISA , OKADA SATOSHI , HASHIMOTO AKINORI , SUZUKI YOICHI , SHOGEN KAZUYOSHI , TANAKA SHOJI , SUJIKAI HISASHI , KIMURA TAKESHI , KOJIMA MASAAKI
IPC分类号： H03M13/19

7. 发明公开

EP1876717A4 ENCODING APPARATUS AND ENCODING METHOD 审中-公开
标题翻译：编码设备和编码方法
公开(公告)号：EP1876717A4
公开(公告)日：2010-04-28
申请号：EP06745483
申请日：2006-04-20
申请人： SONY CORP
发明人： YOKOKAWA TAKASHI , YAMAMOTO MAKIKO , NAKANE MISA
IPC分类号： H03M13/19
CPC分类号： H03M13/1168 , H03M13/1137 , H03M13/116 , H03M13/1185 , H03M13/6502 , H03M13/6516 , H03M13/6561

8. 发明公开

EP2811703A4 DEMODULATION DEVICE, DEMODULATION METHOD, AND PROGRAM 有权转让
标题翻译：解调，解调和程序
公开(公告)号：EP2811703A4
公开(公告)日：2015-09-30
申请号：EP13743565
申请日：2013-01-25
申请人： SONY CORP
发明人： KAMATA HIROYUKI , HIRAYAMA YUICHI , NAKANE MISA
IPC分类号： H04L27/22 , H03D3/00 , H04L1/00 , H04L27/00 , H04L27/38
CPC分类号： H03D3/007 , H03D2200/005 , H04L1/0047 , H04L27/22 , H04L27/38 , H04L2027/0065
摘要： The present technique relates to a demodulation device, a demodulation method and a program capable of realizing a demodulation process at a rate equivalent to a case where I and Q channel signals are not inverted, even when the I and Q channel signals are inverted. A frequency correction unit establishes synchronization of a frequency and clock based on a signal from a frequency synchronization unit. A channel inversion detection unit of a frame synchronization unit detects presence or absence of inversion of I and Q channel signals, and supplies, as a detection result, a channel inversion detection result to the channel inversion control unit. The channel inversion control unit switches the I and Q channel signals if the inversion has occurred, based on the channel inversion detection result. This technique can be applied to a demodulation device.

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