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1. 发明申请

US20110049655A1 PILLAR-BASED INTERCONNECTS FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权
标题翻译：用于磁阻随机存取存储器的基于柱状的互连
公开(公告)号：US20110049655A1
公开(公告)日：2011-03-03
申请号：US12549799
申请日：2009-08-28
申请人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Eugene J. O'Sullivan
发明人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Eugene J. O'Sullivan
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
摘要翻译：半导体器件包括包括M2图案化区域的衬底。在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。

2. 发明授权

US08884387B2 Pillar-based interconnects for magnetoresistive random access memory 有权
标题翻译：用于磁阻随机存取存储器的基于柱的互连
公开(公告)号：US08884387B2
公开(公告)日：2014-11-11
申请号：US13568670
申请日：2012-08-07
申请人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Eugene J. O'Sullivan
发明人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Eugene J. O'Sullivan
IPC分类号： H01L29/82 , H01L27/22 , H01L43/12 , H01L43/08
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
摘要翻译：半导体器件包括包括M2图案化区域的衬底。在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。

3. 发明授权

US08796041B2 Pillar-based interconnects for magnetoresistive random access memory 有权
公开(公告)号：US08796041B2
公开(公告)日：2014-08-05
申请号：US12549799
申请日：2009-08-28
申请人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Eugene J. O'Sullivan
发明人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Eugene J. O'Sullivan
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.

4. 发明授权

US07755921B2 Method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices 有权
标题翻译：用于制造用于磁移位寄存器存储器件的亚光刻数据轨迹的方法和装置
公开(公告)号：US07755921B2
公开(公告)日：2010-07-13
申请号：US11838663
申请日：2007-08-14
申请人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Stuart Stephen Papworth Parkin , Christy S. Tyberg
发明人： Solomon Assefa , Michael C. Gaidis , Eric A. Joseph , Stuart Stephen Papworth Parkin , Christy S. Tyberg
IPC分类号： G11C19/00
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C19/0808 , H01L21/76816 , H01L43/08
摘要： In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section.
摘要翻译：在一个实施例中，本发明是用于制造用于磁移位寄存器存储器件的子光刻数据磁道的方法和装置。存储器件的一个实施例包括由第一电介质材料形成的介电材料的第一叠层，围绕第一电介质材料堆叠并由至少第二电介质材料形成的第二电介质材料叠层，以及至少一个用于存储位于所述第一电介质材料堆叠和所述第二电介质材料堆之间的信息，所述数据轨道具有高纵横比和基本上矩形的横截面。

5. 发明申请

US20090046493A1 METHOD AND APPARATUS FOR FABRICATING SUB-LITHOGRAPHY DATA TRACKS FOR USE IN MAGNETIC SHIFT REGISTER MEMORY DEVICES 有权
标题翻译：用于制作用于磁移位置存储器件的次数据轨迹的方法和装置
公开(公告)号：US20090046493A1
公开(公告)日：2009-02-19
申请号：US11838663
申请日：2007-08-14
申请人： SOLOMON ASSEFA , Michael C. Gaidis , Eric A. Joseph , Stuart Stephen Papworth Parkin , Christy S. Tyberg
发明人： SOLOMON ASSEFA , Michael C. Gaidis , Eric A. Joseph , Stuart Stephen Papworth Parkin , Christy S. Tyberg
IPC分类号： G11C19/08 , H01L21/00
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C19/0808 , H01L21/76816 , H01L43/08
摘要： In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section.
摘要翻译：在一个实施例中，本发明是用于制造用于磁移位寄存器存储器件的子光刻数据磁道的方法和装置。存储器件的一个实施例包括由第一电介质材料形成的介电材料的第一叠层，围绕第一电介质材料堆叠并由至少第二电介质材料形成的第二电介质材料叠层，以及至少一个用于存储位于所述第一电介质材料堆叠和所述第二电介质材料堆之间的信息，所述数据轨道具有高纵横比和基本上矩形的横截面。

6. 发明授权

US07803639B2 Method of forming vertical contacts in integrated circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US07803639B2
公开(公告)日：2010-09-28
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

7. 发明申请

US20080211055A1 Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit 审中-公开
标题翻译：利用侧壁间隔件在集成电路中形成磁隧道结
公开(公告)号：US20080211055A1
公开(公告)日：2008-09-04
申请号：US12120915
申请日：2008-05-15
申请人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
发明人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
IPC分类号： H01L43/00 , H01L43/12
CPC分类号： H01L43/12 , H01L27/222
摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.
摘要翻译：描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

8. 发明授权

US07531367B2 Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit 有权
标题翻译：利用侧壁间隔物特征在集成电路中形成磁隧道结
公开(公告)号：US07531367B2
公开(公告)日：2009-05-12
申请号：US11333997
申请日：2006-01-18
申请人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
发明人： Solomon Assefa , Michael C. Gaidis , Sivananda Kanakasabapathy , John P. Hummel , David W. Abraham
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/222
摘要： Novel methods for reliably and reproducibly forming magnetic tunnel junctions in integrated circuits are described. In accordance with aspects of the invention, sidewall spacer features are utilized during the processing of the film stack. Advantageously, these sidewall spacer features create a tapered masking feature which helps to avoid byproduct redeposition during the etching of the MTJ film stack, thereby improving process yield. Moreover, the sidewall spacer features may be used as encapsulating layers during subsequent processing steps and as vertical contacts to higher levels of metallization.
摘要翻译：描述了在集成电路中可靠且可重复地形成磁隧道结的新方法。根据本发明的方面，在膜叠层的处理期间利用侧壁间隔物特征。有利地，这些侧壁间隔物特征产生锥形掩蔽特征，其有助于避免在MTJ膜叠层的蚀刻期间的副产物再沉积，从而提高工艺产率。此外，侧壁间隔物特征可以在随后的处理步骤期间用作包封层，并且可以用作垂直接触以进行更高级别的金属化。

9. 发明申请

US20080164617A1 Method of Forming Vertical Contacts in Integrated Circuits 有权
标题翻译：在集成电路中形成垂直触点的方法
公开(公告)号：US20080164617A1
公开(公告)日：2008-07-10
申请号：US11619623
申请日：2007-01-04
申请人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
发明人： Solomon Assefa , Michael C. Gaidis , John P. Hummel , Sivananda K. Kanakasabapathy
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L43/12 , H01L21/76807 , H01L21/76816
摘要： A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.
摘要翻译：在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。形成覆盖在第一和第二蚀刻停止层上的ILD层。在ILD层上形成光刻掩模。光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。

10. 发明申请

US20080185101A1 Hard Mask Structure for Patterning of Materials 有权
标题翻译：材料图案的硬掩模结构
公开(公告)号：US20080185101A1
公开(公告)日：2008-08-07
申请号：US12099441
申请日：2008-04-08
申请人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
发明人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
IPC分类号： H01L21/306
CPC分类号： H01L43/12 , H01L21/0332 , H01L21/0337 , H01L27/11507 , H01L28/65
摘要： Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.
摘要翻译：提供了磁性器件制造技术。一方面，图案化至少一种，例如非挥发性材料的方法包括以下步骤。在待图案化材料的至少一个表面上形成硬掩模结构。硬掩模结构被配置为具有靠近材料的基部和与基部相对的顶部。基座具有大于硬掩模结构的顶部的一个或多个横向尺寸的一个或多个横向尺寸，使得基部的至少一部分横向延伸超过顶部的实质距离。硬掩模结构的顶部距离被蚀刻的材料比基底更大的垂直距离。材料被蚀刻。

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