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1. 发明授权

US06854040B1 Non-volatile memory device with burst mode reading and corresponding reading method 有权
标题翻译：具有突发模式读取的非易失性存储器件和相应的读取方法
公开(公告)号：US06854040B1
公开(公告)日：2005-02-08
申请号：US09717938
申请日：2000-11-21
申请人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonino Geraci , Mauro Sali , Lorenzo Bedarida
IPC分类号： G11C7/10 , G06F12/00 , G06F13/28 , G11C8/04
CPC分类号： G11C7/1072 , G11C7/1033 , G11C7/1045
摘要： A read control circuit and a reading method for an electronic memory device integrated on a semiconductor includes a non-volatile memory matrix with associated row and column decoders connected to respective outputs of an address counter. An address transition detect (ATD) circuit detects an input transition as the memory device is being accessed, and read amplifiers and attendant registers transfer the data read from the memory matrix to the output. The read control circuit includes a detection circuit to which is input a clock signal and a logic signal to enable reading in the burst mode. A burst read mode control logic circuit is connected downstream of the detection circuit. The method includes accessing the memory matrix in a random read mode, detecting a request for access in the burst read mode, and executing the parallel reading of a plurality of memory words during a single period of time clocked by the clock signal.
摘要翻译：集成在半导体上的电子存储装置的读取控制电路和读取方法包括具有连接到地址计数器的相应输出的相关联的行和列解码器的非易失性存储器矩阵。地址转换检测（ATD）电路在正在访问存储器件时检测输入转换，并且读取放大器和伴随寄存器将从存储器矩阵读取的数据传送到输出。读取控制电路包括检测电路，在该检测电路中输入时钟信号和逻辑信号，使得能够以突发模式进行读取。突发读模式控制逻辑电路连接在检测电路的下游。该方法包括以随机读取模式访问存储器矩阵，以突发读取模式检测访问请求，以及在由时钟信号计时的单个时间段内执行多个存储器字的并行读取。

2. 发明授权

US06912598B1 Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read 有权
标题翻译：具有同时修改内容和突发模式读取或页面模式读取功能的非易失性存储器
公开(公告)号：US06912598B1
公开(公告)日：2005-06-28
申请号：US09627703
申请日：2000-07-28
申请人： Lorenzo Bedarida , Antonino Geraci , Mauro Sali , Simone Bartoli
发明人： Lorenzo Bedarida , Antonino Geraci , Mauro Sali , Simone Bartoli
IPC分类号： G11C16/10 , G11C16/26 , G06F9/28 , G06F13/16
CPC分类号： G11C16/10 , G11C16/26
摘要： An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.
摘要翻译：一种电可更改的半导体存储器包括至少两个基本上独立的存储体，以及第一控制电路，用于控制存储器内容的电气改变的操作。第一控制电路允许选择性地执行对至少两个存储体之一的内容的电气改变的操作。存储器还包括第二控制电路，其允许同时对所述至少两个存储器组之一的内容进行电气改变的所述操作，用于读取另一个存储体的内容的突发模式，寻呼模式或标准读取操作。

3. 发明授权

US06963512B2 Autotesting method of a memory cell matrix, particularly of the non-volatile type 失效
标题翻译：存储单元矩阵的自动测试方法，特别是非易失性类型
公开(公告)号：US06963512B2
公开(公告)日：2005-11-08
申请号：US10328721
申请日：2002-12-23
申请人： Antonino Geraci , Alberto Campisi , Lorenzo Bedarida , Simone Bartoli
发明人： Antonino Geraci , Alberto Campisi , Lorenzo Bedarida , Simone Bartoli
IPC分类号： G11C29/44 , G11C29/00
CPC分类号： G11C29/44
摘要： An autotesting method of a cells matrix of a memory device includes the steps of reading the values contained in a plurality of the memory cells, comparing the read values with reference values, signaling mismatch of the read values with the reference values as an error situation, and storing the error situations. In the autotesting method, the reading, comparing, signaling, and storing steps are repeated for all the memory cells in a matrix column. The autotesting method further includes the steps of storing the positions of any columns having at least one error situation, and repeating all of the preceding steps for all the matrix columns.
摘要翻译：存储器件的单元矩阵的自动测试方法包括以下步骤：读取多个存储器单元中包含的值，将读取的值与参考值进行比较，将读取的值与参考值的信令不匹配作为错误情况，并存储错误情况。在自动测试方法中，对矩阵列中的所有存储单元重复读取，比较，信令和存储步骤。自动测试方法还包括存储具有至少一个错误情况的任何列的位置的步骤，并对所有矩阵列重复所有前述步骤。

4. 发明授权

US06320361B2 Buffer device with dual supply voltage for low supply voltage applications 失效
标题翻译：用于低电源电压应用的双电源电压缓冲器件
公开(公告)号：US06320361B2
公开(公告)日：2001-11-20
申请号：US09736984
申请日：2000-12-13
申请人： Vincenzo Dima , Lorenzo Bedarida , Antonino Geraci , Simone Bartoli
发明人： Vincenzo Dima , Lorenzo Bedarida , Antonino Geraci , Simone Bartoli
IPC分类号： G05F140
CPC分类号： G05F3/242
摘要： An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.
摘要翻译：一种具有第一和第二电源电压基准的输出缓冲器装置，该第一参考电压值低于第二电压基准。输出缓冲器件包括第一和第二互补MOS晶体管，这些晶体管串联连接在一个电源电压基准和另一个电压基准之间，栅极端子连接在一起并连接到该缓冲器件的输入端，并且具有漏极连接在一起的端子和缓冲器的输出端子。有利地，第一晶体管连接到第一电源电压基准。此外，输出缓冲器件包括与第一MOS晶体管相同类型的至少一个额外的驱动MOS晶体管，并且放置在第二电源电压基准和缓冲器件的输出端之间。

5. 发明申请

US20130193590A1 SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：包括电压转换器电路的半导体器件及制造半导体器件的方法
公开(公告)号：US20130193590A1
公开(公告)日：2013-08-01
申请号：US13363242
申请日：2012-01-31
申请人： Simone Bartoli , Antonino Geraci , Stefano Sivero , Marco Passerini
发明人： Simone Bartoli , Antonino Geraci , Stefano Sivero , Marco Passerini
IPC分类号： H01L23/49 , H01L21/50
CPC分类号： H01L23/50 , G11C5/147 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05669 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48669 , H01L2224/49113 , H01L2224/73265 , H01L2224/85205 , H03K17/223 , H03K19/0013 , H01L2924/00014 , H01L2924/20752 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.
摘要翻译：半导体器件包括第一接合焊盘，第二接合焊盘，接合到第一和第二接合焊盘中的所选择的接合焊盘的引线，电连接到第一接合焊盘的电源线，以及耦合到第二接合焊盘的电压转换器电路当焊丝接合到第二焊盘上时，电压转换器电路被激活以产生与电压转换器电路通过电线和第二接合焊盘接收的电压不同的内部电源电压，并且提供内部当电线连接到第一接合焊盘以允许电源线通过电线和第一接合焊盘接收电力电压时，电压转换器电路被去激活。

6. 发明授权

US06788586B2 Output buffer for a nonvolatile memory with output signal switching noise reduction, and nonvolatile memory comprising the same 有权
标题翻译：具有输出信号切换噪声降低的非易失性存储器的输出缓冲器和包括该缓冲器的非易失性存储器
公开(公告)号：US06788586B2
公开(公告)日：2004-09-07
申请号：US10161053
申请日：2002-05-30
申请人： Emanuele Confalonieri , Antonino Geraci , Marco Sforzin , Lorenzo Bedarida
发明人： Emanuele Confalonieri , Antonino Geraci , Marco Sforzin , Lorenzo Bedarida
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1051
摘要： Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.
摘要翻译：这里描述的是一个输出缓冲器，它包括一个由上拉晶体管和一个下拉晶体管形成的输出级，它们串联连接在一个设在电源电位的电源线和一个设在地电位的地线之间，中间节点连接到输出缓冲区的输出。输出缓冲器还包括布置在输出缓冲器的输出端和上拉晶体管之间的单向解耦级，用于在输出缓冲器的切换瞬变期间使输出从电源线分离，以防止存在开关噪声后者被传送到输出缓冲器的输出。

7. 发明授权

US06501673B2 Circuit arrangement for the lowering of the threshold voltage of a diode configured transistor 失效
标题翻译：用于降低二极管配置的晶体管的阈值电压的电路布置
公开(公告)号：US06501673B2
公开(公告)日：2002-12-31
申请号：US09881661
申请日：2001-06-13
申请人： Carlo Lisi , Lorenzo Bedarida , Antonino Geraci , Vincenzo Dima
发明人： Carlo Lisi , Lorenzo Bedarida , Antonino Geraci , Vincenzo Dima
IPC分类号： G11C1600
CPC分类号： G11C16/28
摘要： The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.
摘要翻译：本发明涉及一种用于降低二极管配置晶体管的阈值电压的电路装置，该晶体管包括镜晶体管，第一晶体管和第二晶体管，所述反射镜晶体管和所述第一晶体管与电路节点中的栅电极共同，所述第二晶体管以透射二极管配置连接并且放置在所述第一晶体管的栅电极和漏极之间，并且电流源连接到所述第一晶体管的栅电极和所述第二晶体管的漏电极，其特征在于，包括第三晶体管，其被配置为在其栅电极处接收开关信号，并且连接在所述第一晶体管的漏极和栅电极之间。

8. 发明授权

US06462987B2 Direct-comparison reading circuit for a nonvolatile memory array 有权
标题翻译：用于非易失性存储器阵列的直接比较读取电路
公开(公告)号：US06462987B2
公开(公告)日：2002-10-08
申请号：US09930875
申请日：2001-08-15
申请人： Antonino Geraci , Carlo Lisi , Lorenzo Bedarida , Marco Sforzin
发明人： Antonino Geraci , Carlo Lisi , Lorenzo Bedarida , Marco Sforzin
IPC分类号： G11C1606
CPC分类号： G11C7/12 , G11C16/28
摘要： A direct-comparison reading circuit for a nonvolatile memory array having a plurality of memory cells arranged in rows and columns, and at least one bit line, includes at least one array line, selectively connectable to the bit line, and a reference line; a precharging circuit for precharging the array line and reference line at a preset precharging potential; at least one comparator having a first terminal connected to the array line, and a second terminal connected to the reference line; and an equalization circuit for equalizing the potentials of the array line and reference line in the precharging step. In addition, the reading circuit includes an equalization line distinct from the reference line; and controlled switches for connecting, in the precharging step, the equalization line to the array line and to the reference line, and for disconnecting the equalization line from the array line and from the reference line at the end of the precharging step.
摘要翻译：一种用于具有排列成行和列的多个存储单元和至少一个位线的非易失性存储器阵列的直接比较读取电路，包括可选择地连接到位线的至少一个阵列线和参考线; 预充电电路，用于以预设的预充电电位对阵列线和参考线进行预充电; 至少一个比较器具有连接到阵列线的第一端子和连接到基准线的第二端子; 以及用于均衡预充电步骤中的阵列线和参考线的电位的均衡电路。此外，读取电路包括与参考线不同的均衡线; 以及控制开关，用于在预充电步骤中将均衡线连接到阵列线和参考线，并且用于在预充电步骤结束时将均衡线与阵列线和参考线断开。

9. 发明申请

US20080266946A1 METHOD OF MANAGING A MULTILEVEL MEMORY DEVICE AND RELATED DEVICE 有权
标题翻译：管理多个存储器件的方法及相关器件
公开(公告)号：US20080266946A1
公开(公告)日：2008-10-30
申请号：US12109525
申请日：2008-04-25
申请人： Alessandro Magnavacca , Francesco Pipitone , Carlo Lisi , Antonino Geraci
发明人： Alessandro Magnavacca , Francesco Pipitone , Carlo Lisi , Antonino Geraci
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C7/1006 , G11C11/5628 , G11C16/10
摘要： A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.
摘要翻译：存储器具有被组织成单词页面的k级单元阵列，每个存储一串位。存储装置包括输入了N位串的编码电路，并产生相应的k级串。输入有k级串的程序电路，以存储具有k级的c个单元的组。读取电路读取存储在具有k个级别的c个单元组中的数据，并生成k级字符串。输入读取解码电路，其具有从具有k个级别的c个单元的组读取的k级字符串，以生成N位串。每个页面的字被分组成单词组，每个单词包括具有k个级别的c单元的组，以及存储该单词的至少一个剩余位，以及该页面中的其他单词的相应剩余位， c细胞与k水平。

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