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1. 发明授权

US06920546B2 Fusion of processor micro-operations 有权
标题翻译：处理器微操作的融合
公开(公告)号：US06920546B2
公开(公告)日：2005-07-19
申请号：US10217033
申请日：2002-08-13
申请人： Simcha Gochman , Ittai Anati , Zeev Sperber , Robert Valentine
发明人： Simcha Gochman , Ittai Anati , Zeev Sperber , Robert Valentine
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/383
摘要： Methods and systems provide for the fusing of multiple operations into a single micro-operation (uop). A method of decoding a macro-instruction provides for transferring data relating to a first operation from the macro-instruction to a uop. The uop is to be executed by an execution system of a processor. The method further provides for transferring data relating to a second operation from the macro-instruction to the uop.
摘要翻译：方法和系统提供将多个操作融合到单个微操作（uop）中。解码宏指令的方法提供将与第一操作有关的数据从宏指令传送到uop。 uop将由处理器的执行系统执行。该方法还提供将与第二操作有关的数据从宏指令传送到uop。

2. 发明授权

US07206921B2 Micro-operation un-lamination 有权
标题翻译：微操作分层
公开(公告)号：US07206921B2
公开(公告)日：2007-04-17
申请号：US10407468
申请日：2003-04-07
申请人： Zeev Sperber , Robert Valentine , Simcha Gochman
发明人： Zeev Sperber , Robert Valentine , Simcha Gochman
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30145 , G06F9/3836 , G06F9/384 , G06F9/3885
摘要： A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type operands into a laminated micro-operation, and may generate unlamination information for the laminated micro-operation. The second decoder may generate from the laminated micro-operation and the unlamination information two or more micro-operations, where operands of the two or more micro-operations each correspond to a half of one of the SSE operands of the macroinstruction.
摘要翻译：处理器可以包括用于将宏指令解码为微操作的指令解码器。在一些实施例中，指令解码器可以包括第一解码器和第二解码器。第一解码器可以将具有SSE数据类型操作数的宏指令解码为层叠微操作，并且可以生成层叠微操作的未分层信息。第二解码器可以从层叠微操作和非分层信息生成两个或多个微操作，其中两个或多个微操作的操作数分别对应于宏指令的一个SSE操作数中的一个。

3. 发明申请

US20050033942A1 Distribution of architectural state information in a processor across multiple pipeline stages 审中-公开
标题翻译：跨多个流水线阶段在处理器中分布架构状态信息
公开(公告)号：US20050033942A1
公开(公告)日：2005-02-10
申请号：US10637417
申请日：2003-08-08
申请人： Simcha Gochman , Robert Valentine , Rafael Spigelman , Gregory Pribush
发明人： Simcha Gochman , Robert Valentine , Rafael Spigelman , Gregory Pribush
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3855 , G06F9/3863
摘要： Methods and apparatuses for distributing architectural state information in a processor across multiple pipeline stages are described. An architectural value of a register is represented by a historical value added to an update value which is maintained in a non-final pipeline stage. When an instruction requires the architectural value, a calculation is made and that value is inserted into the pipeline for processing. Recovery of both pre- and post-execution architectural state information is made possible by storing both the update value and the operation to take place on that value for each decoded instruction.
摘要翻译：描述了用于在多个流水线级处理器中分布架构状态信息的方法和装置。寄存器的体系结构值由添加到维护在非最终流水线阶段的更新值的历史值表示。当指令需要架构值时，进行计算，并将该值插入流水线进行处理。通过将更新值和对每个解码指令的值进行的操作存储起来，恢复执行前和执行后架构状态信息成为可能。

4. 发明授权

US5964868A Method and apparatus for implementing a speculative return stack buffer 失效
标题翻译：用于实现推测返回堆栈缓冲区的方法和装置
公开(公告)号：US5964868A
公开(公告)日：1999-10-12
申请号：US647752
申请日：1996-05-15
申请人： Simcha Gochman , Nicolas Kacevas , Farah Jubran
发明人： Simcha Gochman , Nicolas Kacevas , Farah Jubran
IPC分类号： G06F9/38 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3842 , G06F9/3863
摘要： A return stack buffer mechanism that uses two separate return stack buffers is disclosed. The first return stack buffer is the Speculative Return Stack Buffer. The Speculative Return Stack Buffer is updated using speculatively fetched instructions. Thus, the Speculative Return Stack Buffer may become corrupted when incorrect instructions are fetched. The second return stack buffer is the Actual Return Stack Buffer. The Actual Return Stack Buffer is updated using information from fully executed branch instructions. When a branch misprediction causes a pipeline flush, the contents of the Actual Return Stack Buffer is copied into the Speculative Return Stack Buffer to correct any corrupted information.
摘要翻译：公开了一种使用两个单独的返回堆栈缓冲器的返回堆栈缓冲机制。第一个返回堆栈缓冲区是推测返回堆栈缓冲区。使用推测读取的指令更新推测返回堆栈缓冲区。因此，当提取不正确的指令时，推测返回堆栈缓冲区可能会损坏。第二个返回堆栈缓冲区是实际返回堆栈缓冲区。使用完全执行的分支指令的信息更新实际返回堆栈缓冲区。当分支错误预测导致管道冲洗时，实际返回堆栈缓冲区的内容将被复制到推测返回堆栈缓冲区以更正任何损坏的信息。

5. 发明授权

US5928352A Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry 失效
标题翻译：用于实现具有表示虚拟地址条目的可变位数的全关联翻译后备缓冲器的方法和装置
公开(公告)号：US5928352A
公开(公告)日：1999-07-27
申请号：US714355
申请日：1996-09-16
申请人： Simcha Gochman , Jacob Doweck
发明人： Simcha Gochman , Jacob Doweck
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/1027 , G06F12/126 , G06F2212/652
摘要： Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes. The physical address array also has a locked bit and an access bit that are used to implement a translation look-aside buffer replacement scheme.
摘要翻译：一些虚拟内存系统允许更多的一个内存页面大小。为了将虚拟页面地址快速翻译成物理页面地址，需要一个多页面大小的翻译后备缓冲区。多页大小翻译后备缓冲区具有虚拟地址阵列和物理地址阵列。虚拟地址阵列具有与接收的虚拟地址进行比较的一组虚拟地址条目。虚拟地址阵列条目具有虚拟地址标记字段，有效位和页大小位。页面大小位定义存储器页面的大小，从而定义虚拟地址中必须与虚拟地址数组中的虚拟地址标记位匹配的位数。有效位表示条目是否有效。当在虚拟地址阵列中检测到命中时，物理地址阵列中的相应条目被激活。物理地址阵列包括物理页面地址和一组页面属性。物理地址阵列还具有用于实现翻译后备缓冲器替换方案的锁定位和访问位。

6. 发明授权

US5842008A Method and apparatus for implementing a branch target buffer cache with multiple BTB banks 失效
标题翻译：用于实现具有多个BTB组的分支目标缓冲器高速缓存的方法和装置
公开(公告)号：US5842008A
公开(公告)日：1998-11-24
申请号：US665516
申请日：1996-06-18
申请人： Simcha Gochman , Nicolas Kacevas
发明人： Simcha Gochman , Nicolas Kacevas
IPC分类号： G06F9/38
CPC分类号： G06F9/3806
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions within a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache with multiple BTB banks that store branch information about previously executed branch instructions. The branch information stored in each bank of the Branch Target Buffer Cache is addressed by the last byte of each branch instruction When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache banks to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an instruction Fetch Unit about the upcoming branch instruction.
摘要翻译：公开了一种计算机处理器中的分支目标缓冲器电路，其预测计算机指令流内的分支指令。分支目标缓冲器电路使用具有多个BTB组的分支目标缓冲器高速缓存，其存储关于先前执行的分支指令的分支信息。存储在分支目标缓冲区高速缓冲存储器的每个存储区中的分支信息由每个分支指令的最后一个字节寻址。当计算机处理器中的指令获取单元获取指令块时，它发送分支目标缓冲器电路指令指针。基于指令指针，分支目标缓冲器电路查找分支目标缓冲区高速缓冲存储区，以查看正在获取的块中的任何指令是否是分支指令。当分支目标缓冲器电路在分支目标缓冲器高速缓存中发现即将到来的分支指令时，分支目标缓冲器电路通知指令提取单元关于即将到来的分支指令。

7. 发明授权

US5379396A Write ordering for microprocessor depending on cache hit and write buffer content 失效
标题翻译：根据缓存命中和写缓冲区内容，为微处理器写入顺序
公开(公告)号：US5379396A
公开(公告)日：1995-01-03
申请号：US777765
申请日：1991-10-11
申请人： Simcha Gochman , Itamar Kazachinsky , Michael Kagan
发明人： Simcha Gochman , Itamar Kazachinsky , Michael Kagan
IPC分类号： G06F12/08 , G06F12/10 , G06F13/16
CPC分类号： G06F12/0804 , G06F12/1045
摘要： An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.
摘要翻译：具有缓存存储器的微处理器的改进提供强而弱的写入顺序模式。微处理器包括用于接收指示外部写入缓冲器是否为空的信号的端子和指示内部写入缓冲器是否为空的内部信号。如果写入缓冲区不为空，并且在写入周期期间发生命中条件，直到缓冲区为空，微处理器的操作将以强排序模式停止。

8. 发明申请

US20070022274A1 Apparatus, system, and method of predicting and correcting critical paths 审中-公开
标题翻译：装置，系统和预测和校正关键路径的方法
公开(公告)号：US20070022274A1
公开(公告)日：2007-01-25
申请号：US11168491
申请日：2005-06-29
申请人： Roni Rosner , Ari Schmorak , Simcha Gochman , Abraham Mendelson , Guillermo Savransky
发明人： Roni Rosner , Ari Schmorak , Simcha Gochman , Abraham Mendelson , Guillermo Savransky
IPC分类号： G06F15/00
CPC分类号： G06F11/3447 , G06F11/3636 , G06F2201/86 , G06F2201/865 , G06F2201/88 , Y02D10/34
摘要： Embodiments of the invention provide a method that includes partitioning a series of instructions of a trace into a plurality of dependency sets before executing the trace; and marking a first group of the dependency sets as critical and a second group of the dependency sets as non-critical Embodiments of the invention also provide a method that may identify a dependency set in the second group, which delays the execution of at least one dependency set in the first group, as a delaying dependency set; counting the number of delays caused by the delaying dependency set; and re-marking the delaying dependency set as critical when a predefined delaying event threshold is reached. Embodiments of the invention also provide apparatus, system, and machine-readable medium thereof
摘要翻译：本发明的实施例提供了一种方法，其包括在执行跟踪之前将一系列的迹线指令划分成多个依赖集; 并且将第一组依赖关系集合标记为关键，并且作为非关键性集合的第二组依赖集作为本发明的非关键实施例还提供了一种方法，其可以识别第二组中的依赖关系集，其延迟执行至少一个依赖关系设置在第一组中，作为延迟依赖集; 对由延迟依赖关系集引起的延迟数进行计数; 并且当达到预定义的延迟事件阈值时，将延迟依赖关系重新标记为关键。本发明的实施例还提供其装置，系统和机器可读介质

9. 发明授权

US5301298A Processor for multiple cache coherent protocols 失效
标题翻译：多高速缓存一致性协议的处理器
公开(公告)号：US5301298A
公开(公告)日：1994-04-05
申请号：US775161
申请日：1991-10-11
申请人： Michael Kagan , Itamar Kazachinsky , Simcha Gochman , Tal Gat
发明人： Michael Kagan , Itamar Kazachinsky , Simcha Gochman , Tal Gat
IPC分类号： G06F12/08 , G06F12/10 , G06F13/14
CPC分类号： G06F12/0859 , G06F12/0815 , G06F12/0864 , G06F12/1045
摘要： An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.
摘要翻译：公开了允许选择回写，直写或一次写入协议的微处理器的改进。引脚连接到接地或Vcc电位以选择直写或回写协议。当该引脚连接到读/写线时，选择一次写入协议。描述两个处理器之间的互连，其允许处理器以最小的胶合逻辑以一次写入协议操作。

10. 发明授权

US5860147A Method and apparatus for replacement of entries in a translation look-aside buffer 失效
标题翻译：用于替换翻译后备缓冲器中的条目的方法和装置
公开(公告)号：US5860147A
公开(公告)日：1999-01-12
申请号：US714894
申请日：1996-09-16
申请人： Simcha Gochman , Jacob Doweck
发明人： Simcha Gochman , Jacob Doweck
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/1027 , G06F12/126 , G06F2212/652
摘要： Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes. The physical address array also has a locked bit and an access bit that are used to implement a translation look-aside buffer replacement scheme.
摘要翻译：一些虚拟内存系统允许更多的一个内存页面大小。为了将虚拟页面地址快速翻译成物理页面地址，需要一个多页面大小的翻译后备缓冲区。多页大小翻译后备缓冲区具有虚拟地址阵列和物理地址阵列。虚拟地址阵列具有与接收的虚拟地址进行比较的一组虚拟地址条目。虚拟地址阵列条目具有虚拟地址标记字段，有效位和页大小位。页面大小位定义存储器页面的大小，从而定义虚拟地址中必须与虚拟地址数组中的虚拟地址标记位匹配的位数。有效位表示条目是否有效。当在虚拟地址阵列中检测到命中时，物理地址阵列中的相应条目被激活。物理地址阵列包括物理页面地址和一组页面属性。物理地址阵列还具有用于实现翻译后备缓冲器替换方案的锁定位和访问位。

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