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    • 2. 发明授权
    • Method and apparatus for implementing a fully-associative translation
look-aside buffer having a variable numbers of bits representing a
virtual address entry
    • 用于实现具有表示虚拟地址条目的可变位数的全关联翻译后备缓冲器的方法和装置
    • US5928352A
    • 1999-07-27
    • US714355
    • 1996-09-16
    • Simcha GochmanJacob Doweck
    • Simcha GochmanJacob Doweck
    • G06F12/10G06F12/12
    • G06F12/1027G06F12/126G06F2212/652
    • Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes. The physical address array also has a locked bit and an access bit that are used to implement a translation look-aside buffer replacement scheme.
    • 一些虚拟内存系统允许更多的一个内存页面大小。 为了将虚拟页面地址快速翻译成物理页面地址,需要一个多页面大小的翻译后备缓冲区。 多页大小翻译后备缓冲区具有虚拟地址阵列和物理地址阵列。 虚拟地址阵列具有与接收的虚拟地址进行比较的一组虚拟地址条目。 虚拟地址阵列条目具有虚拟地址标记字段,有效位和页大小位。 页面大小位定义存储器页面的大小,从而定义虚拟地址中必须与虚拟地址数组中的虚拟地址标记位匹配的位数。 有效位表示条目是否有效。 当在虚拟地址阵列中检测到命中时,物理地址阵列中的相应条目被激活。 物理地址阵列包括物理页面地址和一组页面属性。 物理地址阵列还具有用于实现翻译后备缓冲器替换方案的锁定位和访问位。
    • 3. 发明授权
    • Method and apparatus for implementing a branch target buffer cache with
multiple BTB banks
    • 用于实现具有多个BTB组的分支目标缓冲器高速缓存的方法和装置
    • US5842008A
    • 1998-11-24
    • US665516
    • 1996-06-18
    • Simcha GochmanNicolas Kacevas
    • Simcha GochmanNicolas Kacevas
    • G06F9/38
    • G06F9/3806
    • A Branch Target Buffer Circuit in a computer processor that predicts branch instructions within a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache with multiple BTB banks that store branch information about previously executed branch instructions. The branch information stored in each bank of the Branch Target Buffer Cache is addressed by the last byte of each branch instruction When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache banks to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an instruction Fetch Unit about the upcoming branch instruction.
    • 公开了一种计算机处理器中的分支目标缓冲器电路,其预测计算机指令流内的分支指令。 分支目标缓冲器电路使用具有多个BTB组的分支目标缓冲器高速缓存,其存储关于先前执行的分支指令的分支信息。 存储在分支目标缓冲区高速缓冲存储器的每个存储区中的分支信息由每个分支指令的最后一个字节寻址。当计算机处理器中的指令获取单元获取指令块时,它发送分支目标缓冲器电路指令指针。 基于指令指针,分支目标缓冲器电路查找分支目标缓冲区高速缓冲存储区,以查看正在获取的块中的任何指令是否是分支指令。 当分支目标缓冲器电路在分支目标缓冲器高速缓存中发现即将到来的分支指令时,分支目标缓冲器电路通知指令提取单元关于即将到来的分支指令。
    • 8. 发明授权
    • Method and apparatus for replacement of entries in a translation
look-aside buffer
    • 用于替换翻译后备缓冲器中的条目的方法和装置
    • US5860147A
    • 1999-01-12
    • US714894
    • 1996-09-16
    • Simcha GochmanJacob Doweck
    • Simcha GochmanJacob Doweck
    • G06F12/10G06F12/12
    • G06F12/1027G06F12/126G06F2212/652
    • Some virtual memory systems allow more that one memory page size. To quickly translate virtual page addresses into physical page addresses, a multi-page size translation look-aside buffer is needed. The multi-page size translation look-aside buffer has a virtual address array and a physical address array. The virtual address array has a set of virtual address entries that are compared to a received virtual address. The virtual address array entries have virtual address tag field, a valid bit, and a page size bit. The page size bit defines the size of the memory page and thus defines the number of bits in the virtual address that must be matched with virtual address tag bits in the virtual address array. The valid bit indicates if the entry is valid or not. When a hit is detected in the virtual address array, a corresponding entry in the physical address array is activated. The physical address array comprises a physical page address and a set of page attributes. The physical address array also has a locked bit and an access bit that are used to implement a translation look-aside buffer replacement scheme.
    • 一些虚拟内存系统允许更多的一个内存页面大小。 为了将虚拟页面地址快速翻译成物理页面地址,需要一个多页面大小的翻译后备缓冲区。 多页大小翻译后备缓冲区具有虚拟地址阵列和物理地址阵列。 虚拟地址阵列具有与接收的虚拟地址进行比较的一组虚拟地址条目。 虚拟地址阵列条目具有虚拟地址标记字段,有效位和页大小位。 页面大小位定义存储器页面的大小,从而定义虚拟地址中必须与虚拟地址数组中的虚拟地址标记位匹配的位数。 有效位表示条目是否有效。 当在虚拟地址阵列中检测到命中时,物理地址阵列中的相应条目被激活。 物理地址阵列包括物理页面地址和一组页面属性。 物理地址阵列还具有用于实现翻译后备缓冲器替换方案的锁定位和访问位。