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1. 发明专利

JP2006332641A Split gate nand flash memory structure and array, programming method of the same, erasure method and readout method, and manufacturing method 有权
标题翻译：分离门NAND闪存存储器结构和阵列，其编程方法，擦除方法和读出方法以及制造方法
公开(公告)号：JP2006332641A
公开(公告)日：2006-12-07
申请号：JP2006129291
申请日：2006-05-08
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： WIDJAJA YUNIARTO , COOKSEY JOHN W , CHEN CHANGYUAN , GAO FENG , LIN YA-FEN , LEE DANA
IPC分类号： H01L21/8247 , G11C16/02 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0425 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C2216/18 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： PROBLEM TO BE SOLVED: To improve the pitch of a nonvolatile memory device by reducing the number of lines for each cell, in a NAND flash memory structure. SOLUTION: A split gate NAND flash memory structure is formed on a first conductive type semiconductor substrate. This NAND structure is provided with a first region of a second conductive type in the substrate; and a second region of a second conductive type, that is spaced apart from the first region in the substrate. A first channel region that is continuous is defined between the first region and the second region. A plurality of floating gates are spaced apart from each another, and each of a plurality of floating gates is arranged on the separate parts of the channel region. There are provided a plurality of control gates that are each associated with one floating gate and adjacent to the floating gate. Each control gate has two parts, that is, a first part located on the part of the channel region and a second part, located on the associated floating gate and capacitively connected to the floating gate. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过减少NAND单元中的线数来提高非易失性存储器件的间距，在NAND闪速存储器结构中。解决方案：在第一导电类型半导体衬底上形成分裂栅极NAND闪速存储器结构。该NAND结构在衬底中设置有第二导电类型的第一区域; 以及与衬底中的第一区域间隔开的第二导电类型的第二区域。在第一区域和第二区域之间限定连续的第一沟道区域。多个浮动栅极彼此间隔开，并且多个浮动栅极中的每一个布置在沟道区域的分离部分上。提供了多个控制栅极，每个控制栅极与一个浮动栅极相关联并且与浮动栅极相邻。每个控制栅极具有两个部分，即位于沟道区域的一部分上的第一部分和位于相关联的浮动栅极上并电容连接到浮动栅极的第二部分。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2009060100A Non-volatile dram with floating gate and its operating method 审中-公开
标题翻译：具有浮动门的非挥发性DRAM及其操作方法
公开(公告)号：JP2009060100A
公开(公告)日：2009-03-19
申请号：JP2008206358
申请日：2008-07-11
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： WIDJAJA YUNIARTO , LEE DANA
IPC分类号： H01L27/105 , G11C14/00 , G11C16/04 , H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10802 , H01L27/105 , H01L27/108 , H01L27/10844 , H01L27/115 , H01L27/11517 , H01L29/42324 , H01L29/7841 , H01L29/7881
摘要： PROBLEM TO BE SOLVED: To provide a DRAM cell with a floating gate storing the state of the DRAM cell in a power-off state and in a power-on or power-restored state, restoring the state from the gate onto the DRAM cell. SOLUTION: A non-volatile capacitor-less 1T DRAM has a semiconductor substrate of a first conducting type with a surface. A first region of a second conducting type is in the substrate on the surface. A second region of the second conducting type is in the substrate on the surface spaced apart from the first region. A body region of the first conducting type is in the substrate between the first region and the second region. The body region is bound by the surface, one or more insulating regions and the first and second regions. The DRAM further has a floating gate insulated from the surface and is positioned between the first and second regions. A control gate is capacitively coupled to the floating gate. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了向DRAM单元提供将DRAM单元的状态存储在断电状态和处于通电或电源恢复状态的浮动栅极，将状态从门恢复到 DRAM单元。解决方案：非挥发性电容器1T DRAM具有表面具有第一导电类型的半导体衬底。第二导电类型的第一区域在表面上的衬底中。第二导电类型的第二区域在与第一区域间隔开的表面上的衬底中。第一导电类型的主体区域在第一区域和第二区域之间的衬底中。身体区域由表面，一个或多个绝缘区域和第一和第二区域结合。 DRAM还具有与表面绝缘并位于第一和第二区域之间的浮栅。控制栅极电容耦合到浮动栅极。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2007251183A Nonvolatile flash memory cell of single gate 审中-公开
标题翻译：单门非易失性闪存存储单元
公开(公告)号：JP2007251183A
公开(公告)日：2007-09-27
申请号：JP2007103268
申请日：2007-03-13
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： CHEN BOMY , HU YAW WEN , LEE DANA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a floating gate memory device of single poly having the capability of elimination on site and being in conformity with a conventional CMOS process. SOLUTION: A nonvolatile floating gate memory cell having a single polysilicon gate, compatible with conventional logic processes comprises a first conductive type substrate. Second conductive type first and second regions are in the substrate. They are separated from each other. A channel region is formed between them. A first gate is insulated from the substrate, is arranged on the first portion of the channel region and on the first region, and is substantially capacitively coupled with the first region. A second gate is separated from the substrate, is separated from the first gate, is arranged on the second portion of the channel region different from the first portion, and is scarcely or is not superimposed on the second region at all. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有在现场消除能力并且符合常规CMOS工艺的单个聚氨酯的浮动栅极存储器件。解决方案：具有与常规逻辑工艺兼容的单个多晶硅栅极的非易失性浮栅存储器单元包括第一导电型衬底。第二导电类型的第一和第二区域在衬底中。他们彼此分开。在它们之间形成沟道区。第一栅极与衬底绝缘，布置在沟道区域的第一部分上并且在第一区域上，并且与第一区域基本上电容耦合。与第一栅极分离的第二栅极与第一栅极分离设置在与第一部分不同的沟道区域的第二部分上，并且根本不叠加在第二区域上。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2004289162A Semiconductor memory array of floating gate memory cells equipped with embedded floating gate, mountain-shaped floating gate and mountain-shaped channel region 审中-公开
公开(公告)号：JP2004289162A
公开(公告)日：2004-10-14
申请号：JP2004082035
申请日：2004-03-22
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： CHEN BOMY , LEE DANA
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7885
摘要： PROBLEM TO BE SOLVED: To provide an array of floating gate memory cells having a trench formed in the surface of a semiconductor substrate.
SOLUTION: A source region and a drain region are formed beneath a trench along the surface of a substrate, and a nonlinear channel region is formed between them. A floating gate has a lower side part arranged in the trench and an upper side part arranged above the surface of the substrate and having a lateral projection stretching in parallel with the surface of the substrate. The lateral projection is formed by making a cavity at the exposed end part of a sacrifice layer by etching and filling it with polysilicon. A control gate is formed closely to the lateral projection and isolated therefrom. Side wall of the trench intersects the surface of the substrate at an acute angle to form a sharp edge facing the floating gate in the direction opposite to the direction of the lateral projection.
COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2013033977A Bidirectional split gate nand flash memory structure and array, programming method thereof, erasing method and reading method, and manufacturing method 有权
标题翻译：双向分割门NAND闪存存储器结构和阵列，其编程方法，擦除方法和读取方法以及制造方法
公开(公告)号：JP2013033977A
公开(公告)日：2013-02-14
申请号：JP2012202682
申请日：2012-09-14
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： GAO FENG , LIN YA-FEN , COOKSEY JOHN W , CHEN CHANGYUAN , WIDJAJA YUNIARTO , LEE DANA
IPC分类号： H01L21/336 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , G11C16/0425 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42328
摘要： PROBLEM TO BE SOLVED: To improve a pitch of a non-volatile memory device by reducing the number of lines for each cell in a NAND flash memory structure.SOLUTION: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises: a first region of a second conductivity type; and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gates is positioned between a pair of floating gates and is capacitively connected to a pair of the floating gates. A plurality of selection gates are spaced apart from one another, with each selection gate insulated from the channel region. Each selection gate is positioned between a pair of the floating gates.
摘要翻译：要解决的问题：通过减少NAND闪存结构中的每个单元的行数来提高非易失性存储器件的间距。解决方案：在第一导电类型的半导体衬底上形成分裂栅极NAND闪速存储器结构。该NAND结构包括：第二导电类型的第一区域; 以及在所述基板中的与所述第一区域间隔开的所述第二导电类型的第二区域，从而在其间限定沟道区域。多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。每个控制栅极位于一对浮动栅极之间，并且电容连接到一对浮动栅极。多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。每个选择门位于一对浮动门之间。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2005303294A Array without contact point and isolation of nonvolatile memory cell, each having floating gate for charge storage, and manufacturing method and its usage 审中-公开
标题翻译：不具有接触点和分离非易失性存储器单元的阵列，每个存储器具有用于充电储存的浮动门，以及制造方法及其使用
公开(公告)号：JP2005303294A
公开(公告)日：2005-10-27
申请号：JP2005108659
申请日：2005-04-05
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： LEE DANA , TRAN HIEU VAN , FRAYER JACK
IPC分类号： H01L21/8247 , G11C16/04 , G11C16/14 , H01L21/28 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7881 , G11C16/0433 , G11C16/0458 , G11C16/0491 , G11C16/14 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： PROBLEM TO BE SOLVED: To provide a compact array of a floating gate nonvolatile memory cell without contact points and isolation, and to provide its manufacturing method and its operation mode. SOLUTION: An array of a floating gate nonvolatile memory cell without a contact point and an isolation has a plurality of memory cells (112), each having a floating gate (22) for storing a charge arrayed in many rows and columns on a semiconductor substrate (50). All bit lines (16) and source lines (20) are embedded, having no contact point. In the first embodiment, each cell is represented by a transistor having laminate of a transistor gate (14) and a control gate (24) connected to another auxiliary transistor. All arrays may be formed into a planar shape, or preferably, each floating gate transistor is located inside a trench (58), or each auxiliary transistor is located inside a trench. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种不具有接触点和隔离的浮动非易失性存储单元的紧凑型阵列，并提供其制造方法及其操作模式。解决方案：没有接触点和隔离的浮动非易失性存储单元的阵列具有多个存储单元（112），每个存储单元具有浮置栅极（22），用于存储排列成许多行和列的电荷半导体衬底（50）。所有位线（16）和源极线（20）都被嵌入，没有接触点。在第一实施例中，每个单元由具有连接到另一个辅助晶体管的晶体管栅极（14）和控制栅极（24））的晶体管表示。所有阵列可以形成为平面形状，或者优选地，每个浮栅晶体管位于沟槽（58）内，或者每个辅助晶体管位于沟槽内。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2004312020A Bidirectional reading/programming nonvolatile floating gate memory cell, its array and fabricating method 有权
公开(公告)号：JP2004312020A
公开(公告)日：2004-11-04
申请号：JP2004112442
申请日：2004-04-06
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： CHEN BOMY , FRAYER JACK , LEE DANA
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0458 , H01L27/115 , H01L29/42336 , H01L29/7887
摘要： PROBLEM TO BE SOLVED: To provide a high density, bidirectional reading/programming nonvolatile memory cell and its array. SOLUTION: Each memory cell (15) has two separated floating gates (40a, 40b) capable of storing charges, and source/drain regions (52a, 52b) separated by a channel. The channel has three parts where one floating gate exists above the first part, the other floating gate exists above the second part, and a gate electrode (62) controls conduction at the third part of the channel located between the first and second parts. Control gates (54a, 54b) are connected with the source/drain regions, respectively, and coupled capacitively with the floating gate. A cell is programmed by hot channel electron injection and erased by Fowler Nordheim tunneling of electrons from the floating gate to the gate electrode. Such a program as the cell stores 1 bit in each floating gate by bidirectional reading is thereby realized. COPYRIGHT: (C)2005,JPO&NCIPI

8. 发明专利

JP2004312019A Nonvolatile floating gate memory cell having floating gate formed in recess, its array and fabricating method 有权
公开(公告)号：JP2004312019A
公开(公告)日：2004-11-04
申请号：JP2004112323
申请日：2004-04-06
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： CHEN BOMY , LEE DANA , YEH BING
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0458 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L29/42324 , H01L29/66825
摘要： PROBLEM TO BE SOLVED: To provide a high density, bidirectional reading/programming nonvolatile memory cell and its array. SOLUTION: The nonvolatile memory cell (60) has source/drain regions (40a, 40b), a channel region (70) consisting of a first part, a second part and a third part, a control gate electrode (54), and first and second conductive or nonconductive floating gates (36a, 36b) for storing charges formed in a semiconductor substrate (10). The floating gate has a substantially triangular shape having three pointed ends (62, 64, 66) formed in a recess. The gate electrode is coupled capacitively with the floating gate. COPYRIGHT: (C)2005,JPO&NCIPI

9. 发明专利

JP2006332640A Bidirectional split gate nand flash memory structure, array, programming method of the same, erasing method, readout method and manufacturing method 有权
标题翻译：双向分闸门NAND闪存存储器结构，阵列，其编程方法，擦除方法，读出方法和制造方法
公开(公告)号：JP2006332640A
公开(公告)日：2006-12-07
申请号：JP2006129028
申请日：2006-05-08
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： GAO FENG , LIN YA-FEN , COOKSEY JOHN W , CHEN CHANGYUAN , WIDJAJA YUNIARTO , LEE DANA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42336 , G11C16/0425 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11556 , H01L29/42328
摘要： PROBLEM TO BE SOLVED: To improve the pitch of a nonvolatile memory device by reducing the number of lines of each cell in a NAND flash memory structure. SOLUTION: A split gate NAND flash memory structure is formed on a first conductive type semiconductor substrate. This NAND structure is provided with: a first region of a second conductive type; and a second region of a second conductive type spaced apart from the first region in the substrate and defining a channel region in a space with the first region. A plurality of floating gates that are each insulated from the channel region are spaced apart from one another. A plurality of control gates that are each insulated from the channel region are spaced apart from one another. Each of the control gates is located between a pair of floating gates and capacitively connected with a pair of floating gates. A plurality of selecting gates that are each insulated from the channel region are spaced apart from one another. Each of the selecting gates is located between a pair of the floating gates. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过减少NAND闪存结构中的每个单元的行数来提高非易失性存储器件的间距。解决方案：在第一导电类型半导体衬底上形成分裂栅极NAND闪速存储器结构。该NAND结构设置有：第二导电类型的第一区域; 以及第二导电类型的第二区域，与衬底中的第一区域间隔开并且在与第一区域的空间中限定沟道区域。与沟道区域绝缘的多个浮动栅极彼此间隔开。与沟道区域绝缘的多个控制栅极彼此间隔开。每个控制栅极位于一对浮动栅极之间，并与一对浮动栅极电容连接。与沟道区域绝缘的多个选择栅极彼此间隔开。每个选择门位于一对浮动门之间。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2006114921A Nrom device and its manufacturing method 有权
标题翻译： NROM设备及其制造方法
公开(公告)号：JP2006114921A
公开(公告)日：2006-04-27
申请号：JP2005322821
申请日：2005-10-07
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： CHEN BOMY , LEE DANA , HU YAW WEN , YEH BING
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L21/28114 , H01L27/11568 , H01L29/66553
摘要： PROBLEM TO BE SOLVED: To form a nonvolatile read only device with a self alignment method.
SOLUTION: A method of forming a memory device (and a device obtained as a result) comprises the steps of: forming an electron trap dielectric material on a substrate; forming a conductive material on the dielectric material; forming a material spacer on the conductive material; forming a segment thereof positioned under the material spacer by removing a part of each of the dielectric material and the conductive material; forming inside the substrate first and second spaced regions having a secondary conductivity type different from that of the substrate; extending a channel region between the first and second regions; controlling a conductivity thereof by positioning the segments of the dielectric material and a first conductive material on the first part of the channel region; forming a second conductive material on the second part of the channel region; and controlling a conductivity thereof so as to be isolated from this second conductive material.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：形成具有自对准方法的非易失性只读器件。解决方案：形成存储器件（以及由此获得的器件）的方法包括以下步骤：在衬底上形成电子阱电介质材料; 在电介质材料上形成导电材料; 在导电材料上形成材料间隔物; 通过去除所述电介质材料和所述导电材料的一部分，形成位于所述材料间隔物下方的段; 在衬底内形成具有不同于衬底的次级导电类型的第一和第二间隔区域; 在第一和第二区域之间延伸通道区域; 通过将介电材料的段和第一导电材料定位在沟道区的第一部分上来控制其导电性; 在所述沟道区域的第二部分上形成第二导电材料; 并控制其导电性，以便与该第二导电材料隔离。版权所有（C）2006，JPO＆NCIPI

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