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1. 发明专利

JP2009044164A Improved split gate type non-volatile flash memory cell and array which have floating gate, control gate, selection gate, and erase gate with overhang on floating gate, and method for manufacturing 有权
标题翻译：改进的分闸门类型非挥发性闪存存储器单元和具有浮动门的控制门，控制门，选择门和具有在浮动门上的过冲的闸门以及制造方法
公开(公告)号：JP2009044164A
公开(公告)日：2009-02-26
申请号：JP2008225276
申请日：2008-08-06
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： LIU XIANG , LEVI AMITAY , KOTOV ALEXANDER , TKACHEV YURI , MARKOV VIKTOR , JIA JAMES YINGBO , SU CHIEN-SHENG , HU YAW WEN
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To improve the efficiency of erasing a cell by the specific dimensional relation of an erase gate with a floating gate.
SOLUTION: An improved split gate type non-volatile memory cell having in a substrate a second conductivity first region, a second conductivity second region, and a channel region between the first region and the second region is formed in a substantially single crystal substrate of the first conductivity type. The cell has a selection gate on the upper portion of the channel region, a floating gate on another portion of the channel, a control gate on the floating gate, and an erase gate adjoining the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang against the dimension of a separation in the vertical direction between the floating gate and the erase gate is in between about 1.0 and 2.5.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过擦除栅极与浮动栅极的特定尺寸关系来提高擦除单元的效率。解决方案：在基板中具有第二导电性第一区域，第二导电性第二区域和第一区域与第二区域之间的沟道区域的改进的分离栅极型非易失性存储单元形成为基本单晶第一导电类型的衬底。信道在信道区域的上部具有选择栅极，沟道的另一部分上的浮动栅极，浮置栅极上的控制栅极以及与浮动栅极相邻的擦除栅极。擦除栅极具有在浮动栅极上延伸的突出端。悬垂尺寸与浮动栅极和擦除栅极之间的垂直方向上的间隔尺寸的比率在约1.0和2.5之间。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2007251183A Nonvolatile flash memory cell of single gate 审中-公开
标题翻译：单门非易失性闪存存储单元
公开(公告)号：JP2007251183A
公开(公告)日：2007-09-27
申请号：JP2007103268
申请日：2007-03-13
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： CHEN BOMY , HU YAW WEN , LEE DANA
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L27/11558 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a floating gate memory device of single poly having the capability of elimination on site and being in conformity with a conventional CMOS process. SOLUTION: A nonvolatile floating gate memory cell having a single polysilicon gate, compatible with conventional logic processes comprises a first conductive type substrate. Second conductive type first and second regions are in the substrate. They are separated from each other. A channel region is formed between them. A first gate is insulated from the substrate, is arranged on the first portion of the channel region and on the first region, and is substantially capacitively coupled with the first region. A second gate is separated from the substrate, is separated from the first gate, is arranged on the second portion of the channel region different from the first portion, and is scarcely or is not superimposed on the second region at all. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供具有在现场消除能力并且符合常规CMOS工艺的单个聚氨酯的浮动栅极存储器件。解决方案：具有与常规逻辑工艺兼容的单个多晶硅栅极的非易失性浮栅存储器单元包括第一导电型衬底。第二导电类型的第一和第二区域在衬底中。他们彼此分开。在它们之间形成沟道区。第一栅极与衬底绝缘，布置在沟道区域的第一部分上并且在第一区域上，并且与第一区域基本上电容耦合。与第一栅极分离的第二栅极与第一栅极分离设置在与第一部分不同的沟道区域的第二部分上，并且根本不叠加在第二区域上。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006114921A Nrom device and its manufacturing method 有权
标题翻译： NROM设备及其制造方法
公开(公告)号：JP2006114921A
公开(公告)日：2006-04-27
申请号：JP2005322821
申请日：2005-10-07
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： CHEN BOMY , LEE DANA , HU YAW WEN , YEH BING
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L21/28114 , H01L27/11568 , H01L29/66553
摘要： PROBLEM TO BE SOLVED: To form a nonvolatile read only device with a self alignment method.
SOLUTION: A method of forming a memory device (and a device obtained as a result) comprises the steps of: forming an electron trap dielectric material on a substrate; forming a conductive material on the dielectric material; forming a material spacer on the conductive material; forming a segment thereof positioned under the material spacer by removing a part of each of the dielectric material and the conductive material; forming inside the substrate first and second spaced regions having a secondary conductivity type different from that of the substrate; extending a channel region between the first and second regions; controlling a conductivity thereof by positioning the segments of the dielectric material and a first conductive material on the first part of the channel region; forming a second conductive material on the second part of the channel region; and controlling a conductivity thereof so as to be isolated from this second conductive material.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：形成具有自对准方法的非易失性只读器件。解决方案：形成存储器件（以及由此获得的器件）的方法包括以下步骤：在衬底上形成电子阱电介质材料; 在电介质材料上形成导电材料; 在导电材料上形成材料间隔物; 通过去除所述电介质材料和所述导电材料的一部分，形成位于所述材料间隔物下方的段; 在衬底内形成具有不同于衬底的次级导电类型的第一和第二间隔区域; 在第一和第二区域之间延伸通道区域; 通过将介电材料的段和第一导电材料定位在沟道区的第一部分上来控制其导电性; 在所述沟道区域的第二部分上形成第二导电材料; 并控制其导电性，以便与该第二导电材料隔离。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2005203801A Improved method for programming electron on floating gate of nonvolatile memory cell 审中-公开
标题翻译：用于在非易失性存储单元的浮动门上编程电子的改进方法
公开(公告)号：JP2005203801A
公开(公告)日：2005-07-28
申请号：JP2005033614
申请日：2005-01-13
申请人： Silicon Storage Technology Inc , シリコンストーリッジテクノロージーインコーポレイテッドSilicon Storage Technology, Inc.
发明人： YEH BING , KIANIAN SOHRAB , HU YAW WEN
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a method for improving the programming efficiency of a nonvolatile memory cell which has a floating gate for storing electrons. SOLUTION: The method for programming the cell includes a step for forming an inversion layer in a second part of a channel. An electron flow is generated in a drain region which adjoins the inversion layer, and the electron flow reaches a pinch-off point passing through the inversion layer. The electrons are accelerated through a depletion layer by a magnetic line of force from the floating gate with little dispersion or without the dispersion. Thereby, the electrons are accelerated through an insulator making the floating gate separate from a substrate, and the electrons are injected into the floating gate. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种用于提高具有用于存储电子的浮动栅极的非易失性存储单元的编程效率的方法。解决方案：用于编程单元的方法包括在通道的第二部分中形成反转层的步骤。在与反转层相邻的漏极区域中产生电子流，电子流到达通过反转层的夹断点。电子通过来自浮动栅极的磁力线通过耗尽层加速，几乎没有色散或没有色散。由此，电子通过绝缘体加速，使得浮栅与衬底分离，并且电子被注入浮栅。版权所有（C）2005，JPO＆NCIPI

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