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1. 发明申请

US20060238029A1 DC/DC power converter 有权
标题翻译： DC / DC电源转换器
公开(公告)号：US20060238029A1
公开(公告)日：2006-10-26
申请号：US11112266
申请日：2005-04-22
申请人： Siew Hoon , Norman Culp , Jun Chen , Franco Maloberti
发明人： Siew Hoon , Norman Culp , Jun Chen , Franco Maloberti
IPC分类号： H02J3/14
CPC分类号： H02M3/158 , H02M2001/009 , Y10T307/406 , Y10T307/469
摘要： A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The control scheme operates to store energy in the energy storage element over a first portion of a cycle, such as by ramping up current through an inductor, according to energy requirements of the multiple loads. After storing the energy in the storage element during the first portion of the cycle, the stored energy is delivered consecutively to each of the multiple loads over a subsequent portion of the cycle.
摘要翻译：开关调节系统和控制方案有效地实现了从诸如电感器的共同能量存储元件驱动多个负载。控制方案用于在循环的第一部分上存储能量存储在能量存储元件中，例如通过根据多个负载的能量需求来升高通过电感器的电流。在循环的第一部分期间将能量存储在存储元件中之后，所存储的能量在循环的后续部分上连续传送到多个负载中的每一个。

2. 发明申请

US20060239082A1 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US20060239082A1
公开(公告)日：2006-10-26
申请号：US11112267
申请日：2005-04-22
申请人： Siew Hoon , Franco Maloberti , Jun Chen
发明人： Siew Hoon , Franco Maloberti , Jun Chen
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： H03K17/0822 , H03K17/04206 , H03K17/165
摘要： A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.
摘要翻译：驱动电路包括耦合在输入电源节点和输出节点之间的第一晶体管。第一晶体管根据第二晶体管和第三晶体管的协同操作，以导通状态中的一个工作，以将输出节点与输入电源节点耦合和非导通状态。第二晶体管被耦合以提供控制输入，以响应于提供在第二晶体管的控制输入处的第一输入信号而将第一晶体管驱动到其导通状态。第三晶体管被耦合以响应于在第三晶体管的控制输入处提供的第二输入信号在输出节点处提供输出，第一和第二输入信号彼此不同相。电路耦合在输入电源节点和第一晶体管的控制输入之间，以根据第二晶体管的操作在第一晶体管的控制输入处提供降低的阻抗。

3. 发明授权

US07230452B2 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US07230452B2
公开(公告)日：2007-06-12
申请号：US11112267
申请日：2005-04-22
申请人： Siew Kuok Hoon , Franco Maloberti , Jun Chen
发明人： Siew Kuok Hoon , Franco Maloberti , Jun Chen
IPC分类号： H03K19/0175
CPC分类号： H03K17/0822 , H03K17/04206 , H03K17/165
摘要： A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.
摘要翻译：驱动电路包括耦合在输入电源节点和输出节点之间的第一晶体管。第一晶体管根据第二晶体管和第三晶体管的协同操作，以导通状态中的一个工作，以将输出节点与输入电源节点耦合和非导通状态。第二晶体管被耦合以提供控制输入，以响应于提供在第二晶体管的控制输入处的第一输入信号而将第一晶体管驱动到其导电状态。第三晶体管被耦合以响应于在第三晶体管的控制输入处提供的第二输入信号在输出节点处提供输出，第一和第二输入信号彼此不同相。电路耦合在输入电源节点和第一晶体管的控制输入之间，以根据第二晶体管的操作在第一晶体管的控制输入处提供降低的阻抗。

4. 发明授权

US07400064B2 DC/DC power converter 有权
标题翻译： DC / DC电源转换器
公开(公告)号：US07400064B2
公开(公告)日：2008-07-15
申请号：US11112266
申请日：2005-04-22
申请人： Siew Kuok Hoon , Norman L. Culp , Jun Chen , Franco Maloberti
发明人： Siew Kuok Hoon , Norman L. Culp , Jun Chen , Franco Maloberti
IPC分类号： H02J1/00 , G05F1/56 , H02M3/335
CPC分类号： H02M3/158 , H02M2001/009 , Y10T307/406 , Y10T307/469
摘要： A switching regulation system and control scheme efficiently enables driving multiple loads from a common energy storage element, such as an inductor. The control scheme operates to store energy in the energy storage element over a first portion of a cycle, such as by ramping up current through an inductor, according to energy requirements of the multiple loads. After storing the energy in the storage element during the first portion of the cycle, the stored energy is delivered consecutively to each of the multiple loads over a subsequent portion of the cycle.
摘要翻译：开关调节系统和控制方案有效地实现了从诸如电感器的共同能量存储元件驱动多个负载。控制方案用于在循环的第一部分上存储能量存储在能量存储元件中，例如通过根据多个负载的能量需求来升高通过电感器的电流。在循环的第一部分期间将能量存储在存储元件中之后，所存储的能量在循环的后续部分上连续传送到多个负载中的每一个。

5. 发明申请

US20050104574A1 REGULATED CASCODE CURRENT SOURCE WITH WIDE OUTPUT SWING 有权
标题翻译：具有宽输出开关的调节电流源
公开(公告)号：US20050104574A1
公开(公告)日：2005-05-19
申请号：US10716958
申请日：2003-11-19
申请人： Siew Hoon , Jun Chen
发明人： Siew Hoon , Jun Chen
IPC分类号： G05F3/16 , G05F3/26
CPC分类号： G05F3/262
摘要： System for a current source with enhanced output impedance. A preferred embodiment comprises a cascode current source arranged in a current mirror configuration (such as current source 600) with a pair of level shifters arranged in a source-follower configuration (such as level shifters 505 and 510). The level shifters reduce the compliance voltage of the current source, permitting use in low voltage applications.
摘要翻译：具有增强输出阻抗的电流源系统。优选实施例包括以电流镜配置（例如电流源600）布置成以源跟随器配置（例如电平移位器505和510）布置的一对电平移位器的共源共栅电流源。电平转换器可降低电流源的顺从电压，允许在低电压应用中使用。

6. 发明申请

US20060261840A1 System and method for determining channel mobility 审中-公开
标题翻译：用于确定信道移动性的系统和方法
公开(公告)号：US20060261840A1
公开(公告)日：2006-11-23
申请号：US11131521
申请日：2005-05-18
申请人： Siew Hoon , Jun Chen
发明人： Siew Hoon , Jun Chen
IPC分类号： G01R31/26
CPC分类号： G01R31/2621
摘要： A system and method are provided for determining channel mobility. The system includes a threshold voltage (VT) extractor that extracts the VT associated with a metal oxide semiconductor (MOS) transistor and provides an output signal functionally related to the extracted VT. An oscillator generates an oscillating waveform according to the output signal and a calculator computes an estimate of a channel mobility parameter based on the oscillating waveform. A plurality of the VT extractor and oscillators can be distributed across the wafer to provide an indication of channel mobility for different regions of the wafer.
摘要翻译：提供了一种用于确定信道移动性的系统和方法。该系统包括提取与金属氧化物半导体（MOS）晶体管相关联的V SUB T N的阈值电压（V SUB）提取器，并提供与所提取的功能相关的输出信号 V 。振荡器根据输出信号产生振荡波形，并且计算器基于振荡波形来计算信道移动性参数的估计。多个V SUB提取器和振荡器可以分布在晶片上，以提供晶片的不同区域的沟道迁移率的指示。

7. 外观设计

USD1019259S1 Bottle cap 有权
公开(公告)号：USD1019259S1
公开(公告)日：2024-03-26
申请号：US29911297
申请日：2023-08-31
申请人： Jun Chen
设计人： Jun Chen
摘要： FIG. 1 is a top perspective view of a bottle cap, showing my new design;
FIG. 2 is a bottom perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top view thereof; and,
FIG. 8 is a bottom view thereof.
The dashed broken lines depict portions of the bottle cap that form no part of the claim design.

8. 发明授权

US11569440B2 Making a memoristic array with an implanted hard mask 有权
公开(公告)号：US11569440B2
公开(公告)日：2023-01-31
申请号：US15412076
申请日：2017-01-23
申请人： Yimin Guo , Rongfu Xiao , Jun Chen
发明人： Yimin Guo , Rongfu Xiao , Jun Chen
IPC分类号： H01L43/12 , H01L27/24 , H01L45/00 , H01L27/22
摘要： The invention disclosed a method to make an implanted hard mask with ultra-small dimensions for fabricating integrated nonvolatile random access memory. Instead of directly depositing hard mask material on top of the memory film stack element, we first make ultra-small VIA holes on a pattern transfer molding (PTM) layer using a reverse memory mask, then fill in the hard mask material into the VIA holes within the PTM material. Ultra-small hard mask pillars are formed after removing the PTM material. To improve the adhesion of the hard mask pillars with the underneath memory stack element, a hard mask sustaining element (HMSE) is added below PTM. Due to a better materials adhesion between HMSE and the hard mask, a stronger hard mask array can be formed.

9. 发明申请

US20210343934A1 COMPOSITE MULTI-STACK SEED LAYER TO IMPROVE PMA FOR PERPENDICULAR MAGNETIC PINNING 有权
公开(公告)号：US20210343934A1
公开(公告)日：2021-11-04
申请号：US16865810
申请日：2020-05-04
申请人： Yimin Guo , Rongfu Xiao , Jun Chen
发明人： Yimin Guo , Rongfu Xiao , Jun Chen
IPC分类号： H01L43/10 , H01L43/08 , H01F10/30 , H01F10/32 , H01F10/12
摘要： The invention comprises a novel composite multi-stack seed layer (CMSL) having lattice constant matched crystalline structure with the Co layer in above perpendicular magnetic pinning layer (pMPL) so that an excellent epitaxial growth of magnetic super lattice pinning layer [Co/(Pt, Pd or Ni)]n along its FCC (111) orientation can be achieved, resulting in a significant enhancement of perpendicular magnetic anisotropy (PMA) for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

10. 发明申请

US20210327960A1 BOTTOM-PINNED MAGNETIC RANDOM ACCESS MEMORY HAVING A COMPOSITE SOT STRUCTURE 有权
公开(公告)号：US20210327960A1
公开(公告)日：2021-10-21
申请号：US16849571
申请日：2020-04-15
申请人： RONGFU XIAO , Yimin Guo , Jun Chen
发明人： RONGFU XIAO , Yimin Guo , Jun Chen
IPC分类号： H01L27/22 , H01L43/08 , H01L43/12 , H01L43/02 , G11C11/16
摘要： An ultra-fast magnetic random access memory (MRAM) comprises a three terminal bottom-pinned composite SOT magnetic tunneling junction (bCSOT-MTJ) element including (counting from top to bottom) a magnetic flux guide (MFG) having a very high magnetic permeability, a spin Hall channel (SHC) having a large positive spin Hall angle, an in-plane magnetic memory (MM) layer, a tunnel barrier (TB) layer, and a magnetic pinning stack (MPS) having a synthetic antiparallel coupling pinned by an antiferromagnetic material. The magnetic writing is significantly boosted by a combined effort of enhanced spin orbit torque (SOT) and Lorentz force generated by current-flowing wire (CFW) in the SHC layer and spin transfer torque (STT) by a current flowing through the MTJ stack, and further enhanced by a magnetic close loop formed at the cross section of MFG/SHC/MM tri-layer. Such bCSOT-MTJ element will have a very fast (down to picoseconds) switching speed and consume much less power suitable level 1 or 2 cache application for SMRAM, CPU, GPU and TPU.

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