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    • 2. 发明授权
    • Driver circuit
    • 驱动电路
    • US07230452B2
    • 2007-06-12
    • US11112267
    • 2005-04-22
    • Siew Kuok HoonFranco MalobertiJun Chen
    • Siew Kuok HoonFranco MalobertiJun Chen
    • H03K19/0175
    • H03K17/0822H03K17/04206H03K17/165
    • A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.
    • 驱动电路包括耦合在输入电源节点和输出节点之间的第一晶体管。 第一晶体管根据第二晶体管和第三晶体管的协同操作,以导通状态中的一个工作,以将输出节点与输入电源节点耦合和非导通状态。 第二晶体管被耦合以提供控制输入,以响应于提供在第二晶体管的控制输入处的第一输入信号而将第一晶体管驱动到其导电状态。 第三晶体管被耦合以响应于在第三晶体管的控制输入处提供的第二输入信号在输出节点处提供输出,第一和第二输入信号彼此不同相。 电路耦合在输入电源节点和第一晶体管的控制输入之间,以根据第二晶体管的操作在第一晶体管的控制输入处提供降低的阻抗。
    • 3. 发明授权
    • Bandgap voltage reference insensitive to voltage offset
    • 带隙电压基准对电压偏移不敏感
    • US06690228B1
    • 2004-02-10
    • US10316340
    • 2002-12-11
    • Jun ChenSiew Kuok Hoon
    • Jun ChenSiew Kuok Hoon
    • G05F302
    • G05F3/30
    • A bandgap reference circuit. The circuit includes a first current mirror having a first mirror transistor and a second mirror transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A first bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a predetermined size, is arranged to conduct a collector current from the first mirror transistor. A second bipolar transistor having an emitter, a base, and a collector, wherein the area of the emitter thereof has a size that is proportional to the size of the emitter area of the first bipolar transistor, is arranged to conduct a collector current from the second mirror transistor, the base thereof being connected to the collector thereof. A first resistor is provided, in series with the collector of the second bipolar transistor and the second mirror transistor. The base of the first bipolar transistor is coupled to a common connection node of the first resistor and the second mirror transistor to substantially reduce the effects of offset error in the holding circuit. The holding circuit may be an operational amplifier.
    • 带隙参考电路。 电路包括具有第一反射镜晶体管和第二反射镜晶体管的第一电流镜。 保持电路具有适于通过操作来控制通过第一电流镜的电流的输出,以使其在其第一输入处和第二输入处的电压基本相等。 具有发射极,基极和集电极的第一双极晶体管,其中其发射极的面积具有预定的尺寸,被布置成传导来自第一反射镜晶体管的集电极电流。 具有发射极,基极和集电极的第二双极晶体管,其中其发射极的面积具有与第一双极晶体管的发射极面积的尺寸成比例的尺寸,被布置成将集电极电流从 第二反射镜晶体管,其基极连接到其集电极。 提供与第二双极晶体管和第二反射镜晶体管的集电极串联的第一电阻器。 第一双极晶体管的基极耦合到第一电阻器和第二反射镜晶体管的公共连接节点,以大大减少保持电路中的偏移误差的影响。 保持电路可以是运算放大器。
    • 4. 发明授权
    • Threshold voltage extraction circuit
    • 阈值电压提取电路
    • US06844772B2
    • 2005-01-18
    • US10316495
    • 2002-12-11
    • Siew Kuok HoonJun Chen
    • Siew Kuok HoonJun Chen
    • G05F3/26G05F1/10
    • G05F3/262
    • A threshold voltage extraction circuit. The circuit includes a first current mirror having a first transistor and a second transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A third, MOS transistor having a source and a gate, and a resistor circuit, together adapted to generate a voltage which is a multiple of a source-gate threshold voltage of the third transistor, are coupled to the second transistor and to the first input of the holding circuit. A fourth, MOS transistor coupled to the first transistor and to the second input of the subtracting circuit through a second resistor circuit is adapted to generate a threshold voltage across the second resistor circuit, by the operation of the holding circuit. A second current mirror coupled to the first current mirror is adapted to cause a current to flow through a third resistor circuit that corresponds to the current through the first current mirror to thereby provide an output voltage corresponding to the threshold voltage.
    • 阈值电压提取电路。 电路包括具有第一晶体管和第二晶体管的第一电流镜。 保持电路具有适于通过操作来控制通过第一电流镜的电流的输出,以使其在其第一输入处和第二输入处的电压基本相等。 具有源极和栅极的第三个MOS晶体管和电阻电路一起适于产生作为第三晶体管的源极 - 阈值电压的倍数的电压被耦合到第二晶体管和第一输入端 的保持电路。 通过第二电阻器电路耦合到第一晶体管和减法电路的第二输入端的第四MOS晶体管适于通过保持电路的操作产生跨越第二电阻器电路的阈值电压。 耦合到第一电流镜的第二电流镜适于使电流流过对应于通过第一电流镜的电流的第三电阻器电路,从而提供对应于阈值电压的输出电压。