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    • 10. 发明授权
    • Negative wordline bias for reduction of leakage current during flash memory operation
    • 用于在闪存操作期间减少漏电流的负字线偏置
    • US07463525B2
    • 2008-12-09
    • US11615280
    • 2006-12-22
    • Wei ZhengMeng DingSung-Chul Lee
    • Wei ZhengMeng DingSung-Chul Lee
    • G11C16/06
    • G11C16/0475G11C11/5642G11C16/0491G11C16/3454G11C16/349
    • A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are selected and the appropriate programming voltages are established at their wordlines and bitlines. Unselected wordlines in the array are biased with a slight negative bias voltage to reduce or eliminate leakage bitline current that might otherwise conduct through the memory cells. A slight negative wordline bias voltage may also be applied to unselected cells during verification operations (program verify, soft program verify, erase verify) and read operations to reduce or eliminate leakage current that might otherwise introduce errors in the verification and read operations.
    • 根据本发明的示例性实施例配置的闪存系统采用虚拟接地阵列架构。 在编程操作期间,选择目标存储单元,并在其字线和位线上建立适当的编程电压。 阵列中未选择的字线偏置有轻微的负偏置电压,以减少或消除否则可能通过存储器单元传导的泄漏位线电流。 在验证操作(程序验证,软程序验证,擦除验证)和读取操作期间,也可以向未选择的单元施加轻微的负字线偏置电压,以减少或消除可能在验证和读取操作中引入错误的泄漏电流。