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1. 发明授权

US5432726A Arithmetic unit for quantization/inverse quantigation 失效
标题翻译：用于量化/逆量化的算术单元
公开(公告)号：US5432726A
公开(公告)日：1995-07-11
申请号：US251311
申请日：1994-05-31
申请人： Shun-ichi Kurohmaru , Hisashi Kodama , Toshiyuki Araki , Masaki Toyokura
发明人： Shun-ichi Kurohmaru , Hisashi Kodama , Toshiyuki Araki , Masaki Toyokura
IPC分类号： G06F7/505 , G06F7/00 , G06F7/50 , G06F9/302 , G06F9/305 , G06F9/32 , G06F17/10 , G06T9/00 , H03M7/30 , H04N19/00 , H04N19/42 , H04N19/436 , G06K9/36
CPC分类号： G06F7/5055 , G06F9/3001 , G06F9/30058 , H04N19/45 , H04N19/60
摘要： Two sets of input data A and B are provided. A first selector circuit outputs either the most significant bit of the input data B or the inversion thereof, in accordance with a control signal which has been sent thereto through a control line. An adder adds 1 to the least significant bit of the input data B, and also adds the output from the first selector circuit to all the other bits thereof. A zero-judgment circuit judges whether the input data B is 0 or not, and then, if it is 0, sets a flag to a predetermined value. A selector-control circuit allows a second selector circuit to select the input data B in the case where the least significant bit of the input data A is 1 or the flag from the zero-judgment circuit is set to the predetermined value, and to select, in the other cases, the output from the adder. In this manner, a conditional branch operation required for quantization and inverse quantization of data is executed at high speed, which operation involves either adding 1 to or subtracting 1 from the input data B to output the result, or outputting the input data B, depending on whether the input data B is positive, negative or zero, and also depending on whether the input data A is an even number or an odd number.
摘要翻译：提供两组输入数据A和B。第一选择器电路根据通过控制线发送给它的控制信号输出输入数据B的最高有效位或其反相。加法器将1加到输入数据B的最低有效位，并将第一选择器电路的输出加到其它所有位。零判断电路判断输入数据B是否为0，然后如果为0则将标志设置为预定值。选择器控制电路允许第二选择器电路在输入数据A的最低有效位为1或来自零判断电路的标志被设置为预定值的情况下选择输入数据B，并且选择在其他情况下，来自加法器的输出。以这种方式，高速执行量化和数据逆量化所需的条件分支操作，该操作涉及从输入数据B中加1或减1以输出结果，或输出输入数据B，依赖关于输入数据B是正还是负，还取决于输入数据A是偶数还是奇数。

2. 发明授权

US5299320A Program control type vector processor for executing a vector pipeline operation for a series of vector data which is in accordance with a vector pipeline 失效
标题翻译：程序控制类型向量处理器，用于对与矢量流水线相对应的一系列向量数据执行向量流水线操作
公开(公告)号：US5299320A
公开(公告)日：1994-03-29
申请号：US752787
申请日：1991-08-30
申请人： Kunitoshi Aono , Masaki Toyokura , Toshiyuki Araki , Akihiko Ohtani , Hisashi Kodama , Kiyoshi Okamoto
发明人： Kunitoshi Aono , Masaki Toyokura , Toshiyuki Araki , Akihiko Ohtani , Hisashi Kodama , Kiyoshi Okamoto
IPC分类号： G06F9/345 , G06F9/38 , G06F15/78 , G06F9/30
CPC分类号： G06F15/8076 , G06F9/30036 , G06F9/345 , G06F9/3885
摘要： In a program control type processor for executing plural instructions including a vector pipeline instruction including a data processor for executing a pipeline operation, there is provided a program controller including a program memory, a program counter and a decoder, and is further provided an address generator and a data memory. When the vector pipeline instruction is read out from the program memory and is decoded by the decoder, the program controller stops the program counter and outputs a start signal, and thereafter, controls an operation of the data processor according to the contents of the vector pipeline instruction. The data processor executes the pipeline operation for the data outputted from the data memory by being controlled by the program controller, and the program controller detects completion of the pipeline operation performed in response to the vector pipeline instruction a predetermined number of cycles after receiving the end signal, and thereafter, sequentially executes instructions following the vector pipeline instruction.
摘要翻译：在用于执行包括包括用于执行流水线操作的数据处理器的向量流水线指令的多个指令的程序控制类型处理器中，提供了一种程序控制器，其包括程序存储器，程序计数器和解码器，并且还提供有地址生成器和数据存储器。当从程序存储器中读出向量流水线指令并由解码器解码时，程序控制器停止程序计数器并输出起始信号，然后根据向量管线的内容来控制数据处理器的操作指令。数据处理器通过由程序控制器控制从数据存储器输出的数据执行流水线操作，并且程序控制器在接收到结束之后响应于向量流水线指令检测预定数量的循环执行的流水线操作的完成信号，然后依次执行向量流水线指令之后的指令。

3. 发明授权

US5293596A Multidimensional address generator and a system for controlling the generator 失效
公开(公告)号：US5293596A
公开(公告)日：1994-03-08
申请号：US658154
申请日：1991-02-20
申请人： Masaki Toyokura , Kunitoshi Aono , Toshiyuki Araki
发明人： Masaki Toyokura , Kunitoshi Aono , Toshiyuki Araki
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0207
摘要： A multidimensional address generator for generating one-dimensional addresses respectively corresponding to P.sub.1 .times.P.sub.2 .times. . . . .times.P.sub.N data of a predetermined region of an N-dimensional entire data array (N is a positive integer larger than one) which has Q.sub.1 .times.Q.sub.2 .times. . . . .times.Q.sub.N data (P.sub.1, . . . and P.sub.N and Q.sub.1, . . . and Q.sub.N are positive integers and P.sub.1 .ltoreq.Q.sub.1, . . . and P.sub.N .ltoreq.Q.sub.N). The generator comprises a first to third multiplexers, an adder and a first to Nth accumulating registers. In the generator, the first multiplexer selects one of a first to Nth increments respectively corresponding to a first to Nth directions, in which data to successively be accessed are arranged. Further, the second multiplexer selects one of data stored in the first to Nth accumulating registers, and the third multiplexer selects between the start address and an output of the adder. Moreover, data selected by the first multiplexer is added by the adder to data selected by the second multiplexer, and data selected by the third multiplexer is inputted to the first to Nth accumulating registers. Furthermore, a start address is written to the first to Nth accumulating registers when the address generator is activated. Moreover, the first increment is added to the data held in the first accumulating register in each of Cycles 1 to (P.sub.1 -1) and . . . and Cycles (P.sub.N P.sub.N-1 . . . P.sub.2 -1)P.sub.1 +1 to (P.sub.N P.sub.N-1 . . . P.sub.2 P.sub.1 -1), the first increment is added to the data held in the first accumulating register, and a result is written thereto. Additionally, an nth increment (n=2, 3, . . . , N) is added to the data held in the nth accumulating register, and a result is written to the first to nth accumulating registers, every P.sub.n-1 P.sub.n-2 . . . P.sub.1 cycles during Cycles P.sub.n P.sub.n-1 P.sub.n-2 . . . P.sub.1 to (P.sub.n -1)P.sub.n-1 P.sub.n-2 . . . P.sub.1 and so on. The data finally obtained in the first accumulating register is outputted. Consequently, an operation of accessing a plurality of multidimensional data can be performed easily and quickly.

4. 发明授权

US5278781A Digital signal processing system 失效
标题翻译：数字信号处理系统
公开(公告)号：US5278781A
公开(公告)日：1994-01-11
申请号：US51273
申请日：1993-04-23
申请人： Kunitoshi Aono , Masaki Toyokura , Shiro Sakiyama , Toshiyuki Araki , Masakatsu Maruyama
发明人： Kunitoshi Aono , Masaki Toyokura , Shiro Sakiyama , Toshiyuki Araki , Masakatsu Maruyama
IPC分类号： G06F7/544 , G06F17/10 , G06F7/38
CPC分类号： G06F7/5443 , G06F17/10 , G06F2207/3884
摘要： A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.
摘要翻译：数字信号处理系统包括用于执行流水线处理操作的多个乘法器/累加器。多个乘法器/累加器中的每一个包括乘法部分和加法部分。乘法部分包括用于存储乘法器的N个中间输出的N个流水线寄存器。加法部分包括用于将N + 1个输入的和转换为两个变换输出的华莱士树变换单元和用于将两个变换输出相加的加法器。 N + 1输入包括来自乘法部分的N个中间输出和来自加法器的一个相加输出。

5. 发明授权

US5103419A Circuit for calculating the sum of products of data 失效
标题翻译：计算数据产品总和的电路
公开(公告)号：US5103419A
公开(公告)日：1992-04-07
申请号：US473760
申请日：1990-02-02
申请人： Masaki Toyokura , Kunitoshi Aono , Toshiyuki Araki
发明人： Masaki Toyokura , Kunitoshi Aono , Toshiyuki Araki
IPC分类号： G06F7/544
CPC分类号： G06F7/5443 , G06F7/49994
摘要： A sum-of-products calculating circuit includes a bit extension circuit, wherein the most significant bit of an intermediate result of the multiplication effected by a multiplier is extended from an order one bit of the order higher than that of the most significant bit of the intermediate result of the multiplication to the sign bit of addition input data to an adder, by using the most significant bit of each of two intermediate results of the multiplication effected by a multiplier and the sign bit of each of multiplication input data to the multiplier. The data having the extended data bits are inputted to an adder as addition data for the addition performed therein. Thereby, the number of bits used for representing output data of the multiplier can be equalized with that of bits used for representing input data of the adder by a simple logic circuit without the addition of dummy bits to the addition data. Thus, the component elements of the calculating circuit is substantially reduced in number.
摘要翻译：产品总计算电路包括比特扩展电路，其中由乘法器执行的乘法的中间结果的最高有效位从比该位的最高有效位的顺序的一位高的顺序扩展通过使用由乘法器实现的乘法的两个中间结果中的每一个的最高有效位和乘法输入数据的乘法符号位乘以乘法运算到加法器的相加输入数据的符号位的中间结果。将具有扩展数据位的数据作为加法执行的加法数据输入加法器。因此，用于表示乘法器的输出数据的比特数可以与用于通过简单逻辑电路表示加法器的输入数据的比特的比特相加，而不对加法数据添加伪比特。因此，计算电路的组成元件的数量显着减少。

6. 发明授权

US5499348A Digital processor capable of concurrently executing external memory access and internal instructions 失效
标题翻译：能够同时执行外部存储器访问和内部指令的数字处理器
公开(公告)号：US5499348A
公开(公告)日：1996-03-12
申请号：US266104
申请日：1994-06-27
申请人： Toshiyuki Araki , Kunitoshi Aono , Masaki Toyokura
发明人： Toshiyuki Araki , Kunitoshi Aono , Masaki Toyokura
IPC分类号： G06F9/38
CPC分类号： G06F9/3824
摘要： The digital processor includes an instruction memory, a sequencer, a decoder, and a memory reference control circuit. In case the sequencer reads the external memory reference instruction, the memory reference control circuit serves to fetch an external memory reference instruction signal and an operand of the external memory reference signal delivered from the decoder, hold the operand until the external memory cycle executed by the external memory reference instruction is terminated, and release the operand when the cycle is terminated. The sequencer serves to have succeeding instructions read out continuously while the external memory reference instruction is being executed, and to concurrently execute the read-out instructions when the read-out instructions refer to resources not occupied by the external memory reference instruction, so as to execute the read-out instructions in parallel with the external memory reference instruction, thereby improving the throughput of the total processing.
摘要翻译：数字处理器包括指令存储器，定序器，解码器和存储器参考控制电路。在定序器读取外部存储器参考指令的情况下，存储器参考控制电路用于获取从解码器传送的外部存储器参考指令信号和外部存储器参考信号的操作数，保持操作数直到由外部存储器参考指令终止，并且在循环终止时释放操作数。当执行外部存储器参考指令时，定序器用于连续地读出后续指令，并且当读出指令参考未被外部存储器参考指令占用的资源时，同时执行读出指令，以便执行与外部存储器参考指令并行的读出指令，从而提高总处理的吞吐量。

7. 发明授权

US06501398B2 Variable-length code decoder using barrel shifters and a look-up table 有权
标题翻译：使用桶形移位器和查找表的可变长度码解码器
公开(公告)号：US06501398B2
公开(公告)日：2002-12-31
申请号：US09815269
申请日：2001-03-23
申请人： Masaki Toyokura
发明人： Masaki Toyokura
IPC分类号： H03M700
CPC分类号： H03M7/40 , H03M7/42
摘要： A variable-length code decoder sequentially decodes a series of variable-length codewords included in a bit stream and outputs decoded symbols corresponding to the codewords. The decoder includes an interface section and a decoding section. The interface section accumulates various code lengths of the decoded codewords to obtain a sum. Next, the interface section selects an N-bit contiguous data sequence (where N is a maximum code length of the codewords) from a 2N- or (2N−1)-bit contiguous data sequence, included in the bit stream, in accordance with the sum and outputs the N-bit contiguous data sequence. The decoding section receives the output of the interface section and decodes a codeword included in a combination of the output and a previous output of the interface section by reference to a lookup table, thereby obtaining and outputting a decoded symbol and outputting a code length of the decoded codeword to the interface section.
摘要翻译：可变长度码解码器对包括在比特流中的一系列可变长度码字进行顺序解码，并输出对应于码字的解码符号。解码器包括接口部分和解码部分。接口部分累积解码码字的各种码长以获得和。接下来，接口部分根据比特流中包含的2N或（2N-1）位连续的数据序列，选择N位连续数据序列（其中N是码字的最大码长）并且输出N位连续的数据序列。解码部分接收接口部分的输出，并通过参考查找表对接口部分的输出和先前输出的组合中包括的码字进行解码，从而获得并输出解码符号并输出解码部分的代码长度解码码字到接口部分。

8. 发明授权

US5596518A Orthogonal transform processor 失效
标题翻译：正交变换处理器
公开(公告)号：US5596518A
公开(公告)日：1997-01-21
申请号：US434298
申请日：1995-05-03
申请人： Masaki Toyokura , Kiyoshi Okamoto , Yoshifumi Matsumoto
发明人： Masaki Toyokura , Kiyoshi Okamoto , Yoshifumi Matsumoto
IPC分类号： G06F7/544 , G06F17/14
CPC分类号： G06F17/147 , G06F7/5443
摘要： Stored in each of four coefficient memories are eight elements of each row of a matrix in 4 rows and 8 columns, which matrix consists of absolute values of elements of upper four rows out of an inverse discrete cosine matrix in 8 rows and 8 columns to be subjected to an 8-point IDCT processing. An input element y.sub.ij is supplied in parallel to four multipliers. Each of the four multipliers executes multiplication of an output of the corresponding coefficient memory out of the four coefficient memories, by the input element y.sub.ij. Eight accumulators are disposed for executing, in parallel, accumulation for obtaining eight inner products using results of the four multipliers while restoring signs of the coefficients of the orthogonal transform matrix. An 8-input selector is disposed for successively selecting results of the eight accumulators to supply an inner product w.sub.ij corresponding to the input element y.sub.ij.
摘要翻译：存储在四个系数存储器的每一个中的是四行和八列中矩阵的每一行的八个元素，该矩阵由8行和8列中的反离散余弦矩阵中的上四行的元素的绝对值组成经过8点IDCT处理。输入元素yij并行提供给四个乘法器。四个乘法器中的每一个由输入元件yij执行四个系数存储器中的对应系数存储器的输出的乘法。八个累加器被设置为并行执行累积，以使用四个乘法器的结果来获得八个内积，同时恢复正交变换矩阵的系数的符号。设置8输入选择器，用于连续选择八个累加器的结果，以提供对应于输入元件yij的内积wij。

9. 发明申请

US20080131089A1 Data Recording/Reproducing Device 审中-公开
标题翻译：数据记录/再现装置
公开(公告)号：US20080131089A1
公开(公告)日：2008-06-05
申请号：US11794955
申请日：2006-09-08
申请人： Masaki Toyokura
发明人： Masaki Toyokura
IPC分类号： H04N5/92
CPC分类号： H04N9/8042 , H04N5/85 , H04N21/4147 , H04N21/4341 , H04N21/4385
摘要： A data recording/reproducing device includes a transport stream decoder for decoding a transport stream and outputting a resultant signal; a program stream encoder for obtaining a program stream by encoding the signal output from the transport stream decoder and outputting the program stream; and a system control unit for controlling the transport stream decoder and the program stream encoder to execute TS-PS conversion. In consideration of priority of processing of the TS-PS conversion, the system control unit allows the TS-PS conversion to be executed when both of the transport stream decoder and the program stream encoder are available for the TS-PS conversion.
摘要翻译：数据记录/再现装置包括传输流解码器，用于解码传输流并输出合成信号; 节目流编码器，用于通过对从传输流解码器输出的信号进行编码并输出节目流来获得节目流; 以及用于控制传输流解码器和程序流编码器以执行TS-PS转换的系统控制单元。考虑到TS-PS转换的处理的优先级，当传输流解码器和程序流编码器都可用于TS-PS转换时，系统控制单元允许执行TS-PS转换。

10. 发明授权

US06950462B2 Video encoding apparatus, video encoding method, and frame rate conversion apparatus 失效
标题翻译：视频编码装置，视频编码方法和帧速率转换装置
公开(公告)号：US06950462B2
公开(公告)日：2005-09-27
申请号：US10092725
申请日：2002-03-08
申请人： Akihiro Watabe , Akihiro Otani , Masaki Toyokura
发明人： Akihiro Watabe , Akihiro Otani , Masaki Toyokura
IPC分类号： H04N19/50 , H03M7/36 , H04N19/136 , H04N19/423 , H04N19/426 , H04N19/587 , H04N19/70 , H04B1/66
CPC分类号： H04N19/428 , H04N19/423 , H04N19/61
摘要： When an input picture is inputted to a video interface and stored in a reordering memory, the input time is recorded utilizing a reference time generator and a frame sync signal, and a frame memory to be encoded by an encoding unit is designated using the time information. Therefore, an encoder, which can perform stable encoding even when intervals of vertical sync signals are varied, is realized.
摘要翻译：当将输入图像输入到视频接口并存储在重排序存储器中时，使用参考时间发生器和帧同步信号记录输入时间，并且使用时间信息指定要由编码单元编码的帧存储器。因此，即使在垂直同步信号的间隔变化的情况下也能够进行稳定编码的编码器。

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