专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO0231980A3 CYCLIC PHASE SIGNAL GENERATION FROM A SINGLE CLOCK SOURCE USING CURRENT PHASE INTERPOLATION 审中-公开
标题翻译：使用当前相位插值从单个时钟源产生的循环相位信号
公开(公告)号：WO0231980A3
公开(公告)日：2003-11-06
申请号：PCT/US0131941
申请日：2001-10-12
申请人： SILICON COMM LAB INC , CHIEH-YUAN CHAO , YUMING CAO
发明人： CHIEH-YUAN CHAO , YUMING CAO
IPC分类号： H03K5/08 , H03K5/13 , H03K5/135 , H03K5/15 , G06F5/00
CPC分类号： H03K5/1502 , H03K5/08 , H03K5/131 , H03K5/135
摘要： A system (10) and corresponding method for generating multiple phases within a single clock cycle of an input signal. The method includes the steps of generating a plurality of output signals (clk1-clk4) from an input source signal (clock), where each of the plurality of output signals represents a phase-shifted version of the input signal. Next, a pair of signals (clk_a 36, clk_b 38) from the plural output signals is selected to act as clock signals and to define the operating region within which the multiple phases are bounded.A pair of complementary weighted bias currents (I A, IB) are then provided in response to a control signal, each of the complementary bias currents being used to generate the multiple phases of the invention. The pair of weighted bias currents presented to a node are adjusted in response to the selected clock signals, the selected clock signals operating to adjust the rate of change of the weighted bias currents. Finally, a plurality of signals are provided which represent the frequency difference between the first adjusted weighted bias current and a second frequency.
摘要翻译：一种用于在输入信号的单个时钟周期内产生多个相位的系统（10）和相应的方法。该方法包括从输入源信号（时钟）产生多个输出信号（clk1-clk4）的步骤，其中多个输出信号中的每一个表示输入信号的相移版本。接下来，选择来自多个输出信号的一对信号（clk_a 36，clk_b 38）作为时钟信号，并定义多相界限的工作区域。一对补充加权偏置电流（IA，IB ）响应于控制信号被提供，每个互补偏置电流用于产生本发明的多个相。响应于所选择的时钟信号调整呈现给节点的一对加权偏置电流，所选择的时钟信号用于调整加权偏置电流的变化率。最后，提供表示第一调整加权偏置电流和第二频率之间的频率差的多个信号。

2. 发明授权

US06535029B2 Fully differential continuous-time current-mode high speed CMOS comparator 有权
公开(公告)号：US06535029B2
公开(公告)日：2003-03-18
申请号：US09847837
申请日：2001-05-01
申请人： Shou-Po Shih , Chieh-Yuan Chao , Yuming Cao , Yu-Jen Wu
发明人： Shou-Po Shih , Chieh-Yuan Chao , Yuming Cao , Yu-Jen Wu
IPC分类号： H03K522
CPC分类号： H03K3/356139 , H03K5/2481 , H03K5/249
摘要： A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed. By maintaining the comparator output at a substantially predetermined voltage level during non-operating periods, the switching characteristics of the comparator are enhanced.

3. 发明授权

US06380783B1 Cyclic phase signal generation from a single clock source using current phase interpolation 有权
标题翻译：使用电流相位插值从单个时钟源产生循环相位信号
公开(公告)号：US06380783B1
公开(公告)日：2002-04-30
申请号：US09688536
申请日：2000-10-13
申请人： Chieh-Yuan Chao , Yuming Cao
发明人： Chieh-Yuan Chao , Yuming Cao
IPC分类号： H03H1126
CPC分类号： H03K5/1502 , H03K5/08 , H03K5/131 , H03K5/135
摘要： A system and corresponding method for generating multiple phases within a single clock cycle of an input signal is disclosed. The method includes the steps of generating a plurality of output signals from an input source signal, where each of the plurality of output signals represents a phase-shifted version of the input signal. Next, select a pair of signals from the plurality of output signals to act as clock signals, where the selected pair of clock signals define the operating region within which the multiple phases are bounded. Then, provide a pair of complementary weighted bias currents in response to a control signal, where each of the complementary bias currents is used to generate the multiple phases of the present invention. Thereafter, the pair of weighted bias currents presented to a node are adjusted in response to the selected pair of clock signals, where the selected pair of clock signals operates to adjust the rate of change of the weighted bias currents. Finally, a plurality of signals are provided that represent the frequency difference between the first adjusted weighted bias current and a second frequency.
摘要翻译：公开了一种用于在输入信号的单个时钟周期内产生多个相位的系统和相应的方法。该方法包括以下步骤：从输入源信号产生多个输出信号，其中多个输出信号中的每一个表示输入信号的相移版本。接下来，从多个输出信号中选择一对信号作为时钟信号，其中所选择的一对时钟信号限定多个相位有界的工作区域。然后，响应于控制信号提供一对互补的加权偏置电流，其中每个互补偏置电流用于产生本发明的多个相位。此后，响应于所选择的一对时钟信号调整呈现给节点的一对加权偏置电流，其中所选择的一对时钟信号用于调整加权偏置电流的变化率。最后，提供表示第一调整加权偏置电流和第二频率之间的频率差的多个信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式