会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 5. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120112273A1
    • 2012-05-10
    • US13352415
    • 2012-01-18
    • Takaaki AOKITomofusa Shiga
    • Takaaki AOKITomofusa Shiga
    • H01L27/088
    • H01L29/7813H01L29/0696H01L29/4236H01L29/42368H01L29/66666H01L29/66734H01L29/7803H01L29/7806H01L29/7811H01L29/7828H01L29/8083
    • A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.
    • 半导体器件包括:半导体衬底; 垂直型沟槽栅极MOS晶体管; 肖特基势垒二极管; 多个沟槽具有条纹图案以将内部区域分成第一和第二分离区域; 和每个沟槽中的多晶硅膜。 第一分离区域包括用于提供源极的第一导电类型区域和用于提供沟道区域的第二导电类型层。 第一导电类型区域与第一沟槽相邻。 第一沟槽中的多晶硅膜与栅极布线耦合。 第二沟槽不与第一导电类型区域相邻。 第二沟槽中的多晶硅膜与源极或栅极布线耦合。 第二分离区域中的衬底与用于提供肖特基势垒的源极配线耦合。
    • 6. 发明授权
    • Semiconductor device
    • 半导体器件
    • US09136333B2
    • 2015-09-15
    • US13352415
    • 2012-01-18
    • Takaaki AokiTomofusa Shiga
    • Takaaki AokiTomofusa Shiga
    • H01L27/088H01L29/06H01L29/66H01L29/78H01L29/808H01L29/423
    • H01L29/7813H01L29/0696H01L29/4236H01L29/42368H01L29/66666H01L29/66734H01L29/7803H01L29/7806H01L29/7811H01L29/7828H01L29/8083
    • A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.
    • 半导体器件包括:半导体衬底; 垂直型沟槽栅极MOS晶体管; 肖特基势垒二极管; 多个沟槽具有条纹图案以将内部区域分成第一和第二分离区域; 和每个沟槽中的多晶硅膜。 第一分离区域包括用于提供源极的第一导电类型区域和用于提供沟道区域的第二导电类型层。 第一导电类型区域与第一沟槽相邻。 第一沟槽中的多晶硅膜与栅极布线耦合。 第二沟槽不与第一导电类型区域相邻。 第二沟槽中的多晶硅膜与源极或栅极布线耦合。 第二分离区域中的衬底与用于提供肖特基势垒的源极配线耦合。
    • 8. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08154073B2
    • 2012-04-10
    • US11826206
    • 2007-07-12
    • Takaaki AokiTetsuo FujiiTomofusa Shiga
    • Takaaki AokiTetsuo FujiiTomofusa Shiga
    • H01L29/80
    • H01L29/7813H01L29/0696H01L29/4236H01L29/42368H01L29/66666H01L29/66734H01L29/7803H01L29/7806H01L29/7811H01L29/7828H01L29/8083
    • A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.
    • 半导体器件包括:半导体衬底; 垂直型沟槽栅极MOS晶体管; 肖特基势垒二极管; 多个沟槽具有条纹图案以将内部区域分成第一和第二分离区域; 和每个沟槽中的多晶硅膜。 第一分离区域包括用于提供源极的第一导电类型区域和用于提供沟道区域的第二导电类型层。 第一导电类型区域与第一沟槽相邻。 第一沟槽中的多晶硅膜与栅极布线耦合。 第二沟槽不与第一导电类型区域相邻。 第二沟槽中的多晶硅膜与源极或栅极布线耦合。 第二分离区域中的衬底与用于提供肖特基势垒的源极配线耦合。