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1. 发明申请

US20070291613A1 Signal processing apparatus and method for an optical disc drive 有权
标题翻译：用于光盘驱动器的信号处理装置和方法
公开(公告)号：US20070291613A1
公开(公告)日：2007-12-20
申请号：US11758017
申请日：2007-06-05
申请人： Chia-Wei Liao , Chih-Ching Chen , Yuh Cheng , Ming-Jiou Yu , Kuo-Jung Lan , Chun-Yu Lin , Shiue-Shin Liu , Shu-Hung Chou , Yu-Hsuan Lin
发明人： Chia-Wei Liao , Chih-Ching Chen , Yuh Cheng , Ming-Jiou Yu , Kuo-Jung Lan , Chun-Yu Lin , Shiue-Shin Liu , Shu-Hung Chou , Yu-Hsuan Lin
IPC分类号： G11B7/00
CPC分类号： G11B20/10 , G11B7/0903 , G11B7/0909 , G11B7/0943 , G11B7/1263 , G11B20/10009 , G11B2220/2537
摘要： A signal processing apparatus includes sample and hold units for holding a plurality of analog photo diode signals. A signal holding controller generates control signals to the sample and hold units for holding the analog photo diode signals. Analog adjusting modules adjust the held analog photo diode signals. A multiplexer selectively couples one input end of the multiplexer to the output end of the multiplexer for outputting the adjusted analog photo diode signals. An analog to digital converter converts the adjusted analog photo diode signals into digital photo diode signals.
摘要翻译：信号处理装置包括用于保持多个模拟光电二极管信号的采样和保持单元。信号保持控制器产生用于保持模拟光电二极管信号的采样和保持单元的控制信号。模拟调整模块调节保持的模拟光电二极管信号。复用器选择性地将多路复用器的输入端耦合到多路复用器的输出端，以输出经调整的模拟光电二极管信号。模数转换器将调整后的模拟光电二极管信号转换为数字光电二极管信号。

2. 发明授权

US08451971B2 Communication systems, clock generation circuits thereof, and method for generating clock signal 有权
标题翻译：通信系统，其时钟生成电路以及用于产生时钟信号的方法
公开(公告)号：US08451971B2
公开(公告)日：2013-05-28
申请号：US12407226
申请日：2009-03-19
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/081 , H03L7/087 , H03L7/1974
摘要： A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.
摘要翻译：提供时钟发生电路并且包括锁相环（PLL）和校准器。 PLL被布置成接收第一时钟信号并产生输出时钟信号。 PLL根据控制信号调节输出时钟信号的频率。校准器被布置成接收输出时钟信号和第二时钟信号，在输出时钟信号和第二时钟信号之间执行频率校准，并根据频率校准的结果产生控制信号。

3. 发明申请

US20090167369A1 LVDS OUTPUT DRIVER 审中-公开
标题翻译： LVDS输出驱动器
公开(公告)号：US20090167369A1
公开(公告)日：2009-07-02
申请号：US12146723
申请日：2008-06-26
申请人： Shiue-Shin Liu , Tse-Hsiang Hsu
发明人： Shiue-Shin Liu , Tse-Hsiang Hsu
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0276
摘要： An output driver is disclosed. The output driver has a pair of differential outputs coupled to a first supply voltage via a pair of load devices and comprises a current source, a pair of low voltage transistors, a pair of high voltage transistors, and a resistor. The current source has one end coupled to a second supply voltage. Each of the low voltage transistors has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage signal, and a third terminal. Each of the high voltage transistors has a first terminal coupled to the third terminal of a corresponding one of the low voltage transistors, a second terminal coupled to a bias voltage and a third terminal coupled to the output. The resistor is connected between the third terminals of the high voltage transistors.
摘要翻译：公开了一种输出驱动器。输出驱动器具有通过一对负载装置耦合到第一电源电压的一对差分输出，并且包括电流源，一对低压晶体管，一对高压晶体管和电阻器。电流源具有耦合到第二电源电压的一端。每个低电压晶体管具有耦合到电流源的另一端的第一端子，接收低电压信号的第二端子和第三端子。每个高压晶体管具有耦合到相应的一个低压晶体管的第三端子的第一端子，耦合到偏置电压的第二端子和耦合到输出端的第三端子。电阻器连接在高压晶体管的第三端子之间。

4. 发明申请

US20070047687A1 PHASE DETECTOR AND RELATED PHASE DETECTING METHOD THEREOF 审中-公开
标题翻译：相位检测器及其相关检测方法
公开(公告)号：US20070047687A1
公开(公告)日：2007-03-01
申请号：US11306413
申请日：2005-12-27
申请人： Tse-Hsiang Hsu , Shiue-Shin Liu
发明人： Tse-Hsiang Hsu , Shiue-Shin Liu
IPC分类号： H03D3/24
CPC分类号： H03D13/004
摘要： A phase detector for detecting a phase difference between a first signal and a second signal is disclosed. The phase detector includes: a difference determining module, a phase leading/lagging determining module, and a phase determining module. The difference determining module is used for outputting a pulse having a period in which a logic level of the first signal is different from a logic level of the second signal. The phase leading/lagging determining module is used for outputting an detection signal to identify a phase leading/lagging relationship between the first signal and the second signal. The phase determining module is coupled to the difference determining module and the phase leading/lagging determining module for combining the pulse and the detection signal to output a result signal, wherein the result signal comprises difference and leading/lagging information between the first and the second signal.
摘要翻译：公开了一种用于检测第一信号和第二信号之间的相位差的相位检测器。相位检测器包括：差分确定模块，相位前导/滞后确定模块和相位确定模块。差分确定模块用于输出具有第一信号的逻辑电平与第二信号的逻辑电平不同的周期的脉冲。相位前导/滞后判定模块用于输出检测信号，以识别第一信号和第二信号之间的相位前导/滞后关系。相位确定模块耦合到差分确定模块和相位前导/滞后确定模块，用于组合脉冲和检测信号以输出结果信号，其中结果信号包括第一和第二之间的差分和前进/滞后信息信号。

5. 发明授权

US08169265B2 Phase lock loop circuits 有权
标题翻译：锁相环电路
公开(公告)号：US08169265B2
公开(公告)日：2012-05-01
申请号：US12431842
申请日：2009-04-29
申请人： Shiue-Shin Liu
发明人： Shiue-Shin Liu
IPC分类号： H03L7/00
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： A phase lock loop circuit is provided. A phase frequency detector detects a phase difference between a feedback signal and a reference signal, and generates a phase error signal in response to the detected phase difference. A charge pump consists of at least one core device and outputs a current signal based on the phase error signal. An active loop filter receives and transfers the current signal into a control signal. Operating voltage of the active loop filter is higher than operating voltage of the charge pump. A controlled oscillator receives the control signal and generates an output signal in response to the control signal. A feedback divider receives the output signal to generate the feedback signal.
摘要翻译：提供锁相环电路。相位频率检测器检测反馈信号和参考信号之间的相位差，并且响应于检测到的相位差产生相位误差信号。电荷泵由至少一个核心装置组成，并根据相位误差信号输出电流信号。有源环路滤波器接收并将当前信号传送到控制信号中。有源环路滤波器的工作电压高于电荷泵的工作电压。控制振荡器接收控制信号并响应于控制信号产生输出信号。反馈分频器接收输出信号以产生反馈信号。

6. 发明申请

US20110063002A1 BIAS CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT USING THE SAME 有权
标题翻译：使用相同的偏置电路和相位锁定环路
公开(公告)号：US20110063002A1
公开(公告)日：2011-03-17
申请号：US12757043
申请日：2010-04-09
申请人： Shiue-Shin Liu
发明人： Shiue-Shin Liu
IPC分类号： H03L7/08 , G05F3/02
CPC分类号： G05F3/242 , H03L7/0995
摘要： A bias circuit for generating an output bias current includes a first transistor, a passive component, a second transistor, and a bias current generator. The first transistor has a first node coupled to a first reference voltage, a second node, and a control node. The passive component is coupled between the first reference voltage and the control node of the first transistor. The second transistor has a first node coupled to the control node of the first transistor, a control node coupled to the second node of the first transistor, and a second node for providing the output bias current according to a current passing through the passive component. The bias current generator is coupled to the second node of the first transistor, and implemented for providing the first transistor with a bias current.
摘要翻译：用于产生输出偏置电流的偏置电路包括第一晶体管，无源部件，第二晶体管和偏置电流发生器。第一晶体管具有耦合到第一参考电压的第一节点，第二节点和控制节点。无源部件耦合在第一参考电压和第一晶体管的控制节点之间。第二晶体管具有耦合到第一晶体管的控制节点的第一节点，耦合到第一晶体管的第二节点的控制节点和用于根据通过无源部件的电流提供输出偏置电流的第二节点。偏置电流发生器耦合到第一晶体管的第二节点，并且被实现用于向第一晶体管提供偏置电流。

7. 发明授权

US07706219B2 Signal processing apparatus and method for an optical disc drive 有权
标题翻译：用于光盘驱动器的信号处理装置和方法
公开(公告)号：US07706219B2
公开(公告)日：2010-04-27
申请号：US11758017
申请日：2007-06-05
申请人： Chia-Wei Liao , Chih-Ching Chen , Yuh Cheng , Ming-Jiou Yu , Kuo-Jung Lan , Chun-Yu Lin , Shiue-Shin Liu , Shu-Hung Chou , Yu-Hsuan Lin , Jong-Woei Chen
发明人： Chia-Wei Liao , Chih-Ching Chen , Yuh Cheng , Ming-Jiou Yu , Kuo-Jung Lan , Chun-Yu Lin , Shiue-Shin Liu , Shu-Hung Chou , Yu-Hsuan Lin , Jong-Woei Chen
IPC分类号： G11B7/00
CPC分类号： G11B20/10 , G11B7/0903 , G11B7/0909 , G11B7/0943 , G11B7/1263 , G11B20/10009 , G11B2220/2537
摘要： A signal processing apparatus includes sample and hold units for holding a plurality of analog photo diode signals. A signal holding controller generates control signals to the sample and hold units for holding the analog photo diode signals. Analog adjusting modules adjust the held analog photo diode signals. A multiplexer selectively couples one input end of the multiplexer to the output end of the multiplexer for outputting the adjusted analog photo diode signals. An analog to digital converter converts the adjusted analog photo diode signals into digital photo diode signals.
摘要翻译：信号处理装置包括用于保持多个模拟光电二极管信号的采样和保持单元。信号保持控制器产生用于保持模拟光电二极管信号的采样和保持单元的控制信号。模拟调整模块调节保持的模拟光电二极管信号。复用器选择性地将多路复用器的输入端耦合到多路复用器的输出端，以输出经调整的模拟光电二极管信号。模数转换器将调整后的模拟光电二极管信号转换为数字光电二极管信号。

8. 发明申请

US20090296869A1 COMMUNICATION SYSTEMS, CLOCK GENERATION CIRCUITS THEREOF, AND METHOD FOR GENERATING CLOCK SIGNAL 有权
标题翻译：通信系统，其产生电路及其产生时钟信号的方法
公开(公告)号：US20090296869A1
公开(公告)日：2009-12-03
申请号：US12407226
申请日：2009-03-19
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Jeng-Horng Tsai , Chih-Ching Chen , Chuan Liu , Tse-Hsiang Hsu
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/081 , H03L7/087 , H03L7/1974
摘要： A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.
摘要翻译：提供时钟发生电路并且包括锁相环（PLL）和校准器。 PLL被布置成接收第一时钟信号并产生输出时钟信号。 PLL根据控制信号调节输出时钟信号的频率。校准器被布置成接收输出时钟信号和第二时钟信号，在输出时钟信号和第二时钟信号之间执行频率校准，并根据频率校准的结果产生控制信号。

9. 发明授权

US06894352B2 Single-electron transistor and fabrication method thereof 失效
标题翻译：单电子晶体管及其制造方法
公开(公告)号：US06894352B2
公开(公告)日：2005-05-17
申请号：US10602890
申请日：2003-06-25
申请人： Shu-Fen Hu , Yung-Chun Wu , Wen-Tai Lu , Shiue-Shin Liu , Tiao-Yuan Huang , Tien-Sheng Chao
发明人： Shu-Fen Hu , Yung-Chun Wu , Wen-Tai Lu , Shiue-Shin Liu , Tiao-Yuan Huang , Tien-Sheng Chao
IPC分类号： H01L21/335 , H01L29/76 , H01L27/01
CPC分类号： B82Y10/00 , H01L29/66439 , H01L29/7613 , Y10S438/947 , Y10S977/937
摘要： A method for fabricating a single-electron transistor (SET). A one dimensional channel is formed between source and drain on a silicon-on-insulator substrate, and the separated polysilicon sidewall spacer gates are formed by electron-beam lithographically etching process in a self-aligned manner. Operation of the single-electron transistor with self-aligned polysilicon sidewall spacer gates is achieved by applying external bias to the self-aligned polysilicon sidewall spacer gates to form two potential barriers and a quantum dot capable of storage charges between the two potential barriers. A metal upper gate is finally formed and biased to induce a two-dimensional electron gas (2DEG) and control the energy level of the quantum well. Accordingly, the method of the invention comprises a combination of electron beam (E-beam) lithography with multilayer-aligned direct writing technology, oxidation, and wet etching to form a nanoscale one-dimensional channel between source and drain on a silicon-on-insulator substrate.
摘要翻译：一种用于制造单电子晶体管（SET）的方法。在绝缘体上硅衬底上的源极和漏极之间形成一维沟道，并且以自对准方式通过电子束光刻蚀工艺形成分离的多晶硅侧壁间隔栅极。通过将外部偏置施加到自对准多晶硅侧壁间隔栅上来形成具有自对准多晶硅侧壁间隔栅极的单电子晶体管的操作，以形成两个势垒和能够在两个势垒之间存储电荷的量子点。金属上栅极最终形成并偏置以诱导二维电子气（2DEG）并控制量子阱的能级。因此，本发明的方法包括电子束（E-beam）光刻与多层排列直接写入技术的组合，氧化和湿蚀刻，以在硅 - 硅上形成源极和漏极之间的纳米级一维沟道绝缘体基板。

10. 发明授权

US08526559B2 Communication systems and clock generation circuits thereof with reference source switching 有权
标题翻译：具有参考源切换的通信系统及其时钟发生电路
公开(公告)号：US08526559B2
公开(公告)日：2013-09-03
申请号：US12410502
申请日：2009-03-25
申请人： Kuan-Hua Chao , Shiue-Shin Liu , Tse-Hsiang Hsu
发明人： Kuan-Hua Chao , Shiue-Shin Liu , Tse-Hsiang Hsu
IPC分类号： H03D3/24
CPC分类号： H04L7/0091 , H04B15/02 , H04B2215/067 , H04L7/0083
摘要： A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL generates the output clock signal according to a second clock signal.
摘要翻译：提供了一种用于根据输出时钟信号发送数据的发送器的时钟发生电路。时钟发生电路包括时钟发生器和锁相环（PLL）。时钟发生器产生第一个时钟信号。 PLL最初根据第一个时钟信号产生输出时钟信号。当根据第一时钟信号产生的输出时钟信号的频率不在指定发送器所需的范围内时，PLL根据第二时钟信号产生输出时钟信号。

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