专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06894352B2 Single-electron transistor and fabrication method thereof 失效
标题翻译：单电子晶体管及其制造方法
公开(公告)号：US06894352B2
公开(公告)日：2005-05-17
申请号：US10602890
申请日：2003-06-25
申请人： Shu-Fen Hu , Yung-Chun Wu , Wen-Tai Lu , Shiue-Shin Liu , Tiao-Yuan Huang , Tien-Sheng Chao
发明人： Shu-Fen Hu , Yung-Chun Wu , Wen-Tai Lu , Shiue-Shin Liu , Tiao-Yuan Huang , Tien-Sheng Chao
IPC分类号： H01L21/335 , H01L29/76 , H01L27/01
CPC分类号： B82Y10/00 , H01L29/66439 , H01L29/7613 , Y10S438/947 , Y10S977/937
摘要： A method for fabricating a single-electron transistor (SET). A one dimensional channel is formed between source and drain on a silicon-on-insulator substrate, and the separated polysilicon sidewall spacer gates are formed by electron-beam lithographically etching process in a self-aligned manner. Operation of the single-electron transistor with self-aligned polysilicon sidewall spacer gates is achieved by applying external bias to the self-aligned polysilicon sidewall spacer gates to form two potential barriers and a quantum dot capable of storage charges between the two potential barriers. A metal upper gate is finally formed and biased to induce a two-dimensional electron gas (2DEG) and control the energy level of the quantum well. Accordingly, the method of the invention comprises a combination of electron beam (E-beam) lithography with multilayer-aligned direct writing technology, oxidation, and wet etching to form a nanoscale one-dimensional channel between source and drain on a silicon-on-insulator substrate.
摘要翻译：一种用于制造单电子晶体管（SET）的方法。在绝缘体上硅衬底上的源极和漏极之间形成一维沟道，并且以自对准方式通过电子束光刻蚀工艺形成分离的多晶硅侧壁间隔栅极。通过将外部偏置施加到自对准多晶硅侧壁间隔栅上来形成具有自对准多晶硅侧壁间隔栅极的单电子晶体管的操作，以形成两个势垒和能够在两个势垒之间存储电荷的量子点。金属上栅极最终形成并偏置以诱导二维电子气（2DEG）并控制量子阱的能级。因此，本发明的方法包括电子束（E-beam）光刻与多层排列直接写入技术的组合，氧化和湿蚀刻，以在硅 - 硅上形成源极和漏极之间的纳米级一维沟道绝缘体基板。

2. 发明申请

US20080006908A1 Body-tied, strained-channel multi-gate device and methods of manufacturing same 有权
标题翻译：身体束紧，通道多栅极装置及其制造方法
公开(公告)号：US20080006908A1
公开(公告)日：2008-01-10
申请号：US11483906
申请日：2006-07-10
申请人： Hong-Nien Lin , Horng-Chih Lin , Tiao-Yuan Huang
发明人： Hong-Nien Lin , Horng-Chih Lin , Tiao-Yuan Huang
IPC分类号： H01L29/06 , H01L31/00
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823821 , H01L27/0886 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/7842 , H01L29/7849 , H01L29/7851 , H01L29/78687
摘要： A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.
摘要翻译：公开了鳍FET或其他多栅极晶体管。晶体管包括具有第一晶格常数的半导体衬底和从半导体衬底延伸的半导体鳍片。翅片具有与第一晶格常数不同的第二晶格常数以及顶表面和两个相对的侧表面。晶体管还包括覆盖所述顶表面和所述两个相对侧表面的至少一部分的栅极电介质，以及覆盖所述栅极电介质的至少一部分的栅电极。所得到的通道具有由翅片和衬底之间的晶格失配引起的应变。可以通过选择相应的材料来调节该应变。

3. 发明授权

US06667508B2 Nonvolatile memory having a split gate 失效
标题翻译：具有分离门的非易失性存储器
公开(公告)号：US06667508B2
公开(公告)日：2003-12-23
申请号：US10020916
申请日：2001-12-19
申请人： Horng-Chih Lin , Tiao-Yuan Huang
发明人： Horng-Chih Lin , Tiao-Yuan Huang
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/47 , H01L29/7885
摘要： A novel structure of nonvolatile memory is formed on p type silicon and includes a stacked gate, a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One side of the stacked gate has a source region and the other has a drain region, wherein the surface of the source region includes a thin metal silicide connected with a channel region to form a Schottky barrier. A tilted angle implant with As or P doping is performed on the p type silicon substrate to form a drain region and extend a portion of the drain region to a channel region under the stacked gate. For implanting, an n doped source region is also formed, creating an offset between the source region and the channel region as a result of the tilted angle implant. For programming, the source region is grounded, positive voltage is applied to the drain region and the gate, such that the hot carriers inject into the floating gate through the channel adjacent to the source region.
摘要翻译：在p型硅上形成非易失性存储器的新颖结构，并且包括堆叠栅极，隧道电介质层，浮动栅极（FG），电介质层和控制栅极（CG）。堆叠栅极的一侧具有源极区域，另一侧具有漏极区域，其中源极区域的表面包括与沟道区域连接以形成肖特基势垒的薄金属硅化物。在p型硅衬底上执行具有As或P掺杂的倾斜角度注入以形成漏极区域，并且将漏极区域的一部分延伸到堆叠栅极下方的沟道区域。对于注入，也形成了n掺杂的源极区域，由于倾斜角度注入的结果，在源极区域和沟道区域之间产生偏移。对于编程，源极区域接地，正电压被施加到漏极区域和栅极，使得热载流子通过与源极区域相邻的沟道注入浮置栅极。

4. 发明授权

US5529941A Method for making an integrated circuit structure 失效
标题翻译：制造集成电路结构的方法
公开(公告)号：US5529941A
公开(公告)日：1996-06-25
申请号：US219582
申请日：1994-03-28
申请人： Tiao-Yuan Huang
发明人： Tiao-Yuan Huang
IPC分类号： H01L27/02 , H01L27/092 , H01L21/8234
CPC分类号： H01L27/0922 , H01L27/0266
摘要： A method for making an integrated circuit in accordance with the present invention comprises fabricating at least one functional MOSFET with a hot electron resistant structure including a lightly doped drain, fabricating at least one output MOSFET with an ESD resistant structure including a gate means without associated spacers, and electrically coupling at least one functional MOSFET to at least one output MOSFET. An integrated circuit structure in accordance with the present invention includes at least one functional MOSFET having a hot electron resistant structure including a LDD drain, at least one output MOSFET having an ESD resistant structure including a gate means without associated spacers, and means for electrically coupling the two together. The functional MOSFET includes a gate insulator, a conductive gate region over the gate insulator, spacers along the sidewalls of the gate insulator and conductive gate regions, a pair of LDD regions, and source/drain regions. The output MOSFET includes a gate insulator, a conductive gate region over the gate insulator, and source/drain regions. A further method for making an integrated circuit structure includes the step of creating a plurality of NMOS and PMOS gate structures including at least one NMOS gate structure for an ESD transistor. The method further includes making a PMOS LDD implant, making an NMOS LDD implant, creating spacers on the NMOS and PMOS gate structures, removing the spacers from the NMOS gate structure(s) for an ESD transistor, and making source/drain implants for the NMOS and PMOS gate structures.
摘要翻译：根据本发明的制造集成电路的方法包括制造具有包括轻掺杂漏极的热电子结构的至少一个功能MOSFET，制造具有ESD抗性结构的至少一个输出MOSFET，其包括没有相关间隔物的栅极装置并且将至少一个功能MOSFET电耦合到至少一个输出MOSFET。根据本发明的集成电路结构包括至少一个具有包括LDD漏极的耐热电阻结构的功能MOSFET，至少一个具有ESD抗性结构的输出MOSFET，其包括没有相关间隔物的栅极装置，以及用于电耦合的装置两者在一起。功能MOSFET包括栅极绝缘体，栅极绝缘体上的导电栅极区域，沿着栅极绝缘体和导电栅极区域的侧壁的间隔物，一对LDD区域和源极/漏极区域。输出MOSFET包括栅极绝缘体，栅极绝缘体上的导电栅极区域和源极/漏极区域。制造集成电路结构的另一种方法包括产生包括用于ESD晶体管的至少一个NMOS栅极结构的多个NMOS和PMOS栅极结构的步骤。该方法还包括制造PMOS LDD注入，制造NMOS LDD注入，在NMOS和PMOS栅极结构上产生间隔物，从用于ESD晶体管的NMOS栅极结构去除间隔物，以及为 NMOS和PMOS栅结构。

5. 发明授权

US5418391A Semiconductor-on-insulator integrated circuit with selectively thinned channel region 失效
标题翻译：绝缘体上半导体集成电路具有选择性稀疏的沟道区域
公开(公告)号：US5418391A
公开(公告)日：1995-05-23
申请号：US222139
申请日：1994-03-31
申请人： Tiao-Yuan Huang
发明人： Tiao-Yuan Huang
IPC分类号： H01L21/336 , H01L29/786 , H01L29/78
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78621
摘要： A silicon-on-insulator transistor structure includes a selectively thinned channel region, leaving the source and drain regions relatively thick. The relatively thin channel region provides for full depletion, larger current handling, and thus, faster operation. The relatively thick source and drain regions provide resistance to damage by electrostatic discharge. The transistor structure can be formed from a silicon-on-insulator wafer by performing a light, deep source/drain implant; a shallow, heavy source/drain implant is optionally performed at this stage. Source and drain regions are masked, while the channel regions are etched to the desired channel thickness. After the mask material is removed, a gate oxide can be grown; gates can then be defined. If it has not been performed earlier, the shallow heavy source/drain implant can be performed at this point. In addition, a channel threshold adjust implant can be performed after the channel regions are thinned and before the gates are formed.
摘要翻译：绝缘体上硅晶体管结构包括选择性变薄的沟道区，留下源极和漏极区相对较厚。相对薄的通道区域提供完全耗尽，更大的电流处理，从而更快的操作。相对较厚的源极和漏极区域提供对静电放电损伤的抵抗力。晶体管结构可以通过执行光，深源极/漏极注入而由绝缘体上硅晶片形成; 在这个阶段任选地执行浅的，重的源/漏植入物。源极和漏极区域被掩蔽，而沟道区域被蚀刻到期望的沟道厚度。在去除掩模材料之后，可以生长栅极氧化物; 然后可以定义门。如果以前没有进行过，则可以在此处进行浅重源/漏极植入。此外，可以在沟道区域变薄并且在栅极形成之前执行沟道阈值调整注入。

6. 发明授权

US5386134A Asymmetric electro-static discharge transistors for increased electro-static discharge hardness 失效
标题翻译：不对称静电放电晶体管，提高静电放电硬度
公开(公告)号：US5386134A
公开(公告)日：1995-01-31
申请号：US156156
申请日：1993-11-23
申请人： Tiao-Yuan Huang
发明人： Tiao-Yuan Huang
IPC分类号： H01L27/02 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7835 , H01L27/0266
摘要： An asymmetric electro-static discharge transistor includes a gate region formed on a substrate. The gate region includes a polysilicon gate region placed over a dielectric layer. A drain region is placed within the substrate. The drain region includes a first drain region implanted with atoms of a first conductivity type at a first concentration. The first drain region extends under the gate region. For example, the first drain region is a lightly doped n.sup.- region. A second drain region is formed adjacent to the first doped portion. The second drain region is implanted with atoms of the first conductivity type. For example, the second drain region is a heavily doped n.sup.+ region. A source region is formed within the substrate. The source region extends under the gate region. The source region is implanted with atoms of the first conductivity type. For example, the source region is a heavily doped n.sup.+ region.
摘要翻译：非对称静电放电晶体管包括形成在基板上的栅极区域。栅极区域包括放置在电介质层上的多晶硅栅极区域。漏极区域被放置在衬底内。漏区包括以第一浓度注入第一导电类型的原子的第一漏区。第一漏极区域在栅极区域的下方延伸。例如，第一漏区是轻掺杂的n-区。形成与第一掺杂部分相邻的第二漏区。第二漏极区域注入第一导电类型的原子。例如，第二漏区是重掺杂的n +区。源极区形成在衬底内。源极区域在栅极区域的下方延伸。源区域注入第一导电类型的原子。例如，源极区是重掺杂的n +区。

7. 发明授权

US5998246A Self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain 失效
标题翻译：用于形成单晶底栅和偏移漏极的薄膜晶体管的自对准制造方法
公开(公告)号：US5998246A
公开(公告)日：1999-12-07
申请号：US908721
申请日：1997-08-08
申请人： Tiao-Yuan Huang , Horng-Chih Lin
发明人： Tiao-Yuan Huang , Horng-Chih Lin
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00
CPC分类号： H01L29/66613 , H01L29/66765 , H01L29/78624 , H01L29/78678
摘要： The present invention is related to a self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain. The main object of the present invention is to disclose two manufacturing methods to attain the self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain. In the first method, a photoresistor and a silicon nitride are used to form a dual stack as a mask, further a large-angle ion implant is used to form a thin film transistor with a single-crystal bottom-gate and an offset drain. In the second method, the source side is protected by a dual stack formed by a P+ polysilicon layer which may be discarded selectively and a silicon nitride and an insulation spacer of sidewall in order to selectively discard the silicon nitride on the drain side, thus the object of a thin film transistor with a single-crystal bottom-gate and an offset drain is obtained.
摘要翻译：本发明涉及用于形成单晶底栅和偏移漏极的薄膜晶体管的自对准制造方法。本发明的主要目的是公开用于形成单晶底栅和偏移漏极的薄膜晶体管的自对准制造方法的两种制造方法。在第一种方法中，使用光敏电阻和氮化硅形成双重叠层作为掩模，此外，使用大角度离子注入来形成具有单晶底栅和偏移漏极的薄膜晶体管。在第二种方法中，源极由可以被选择性地丢弃的P +多晶硅层和氮化硅和侧壁的绝缘间隔物形成的双重叠层保护，以便选择性地将漏极侧的氮化硅丢弃，因此，获得具有单晶底栅和偏移漏极的薄膜晶体管的目的。

8. 发明授权

US5814544A Forming a MOS transistor with a recessed channel 失效
标题翻译：形成具有凹陷通道的MOS晶体管
公开(公告)号：US5814544A
公开(公告)日：1998-09-29
申请号：US687294
申请日：1996-07-25
申请人： Tiao-Yuan Huang
发明人： Tiao-Yuan Huang
IPC分类号： H01L21/336 , H01L29/10 , H01L29/423 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66613 , H01L29/1083 , H01L29/42368 , H01L29/7834
摘要： A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel region is recessed. A differential oxide growth then serves to mask the source and the drain for channel threshold adjust and punch-through implants. A doped polysilicon gate is formed, with the thinner area of the differential oxide serving as the gate oxide. In the resulting structure, the punch-through dopant is spaced from the source and the drain, reducing parasitic capacitance and improving transistor switching speeds.
摘要翻译：通过形成由较低二氧化硅层和上部氮化硅层构成的反向栅极掩模来制造MOS晶体管。暴露的通道区域被热氧化。去除掩模以允许源/漏植入。去除氧化物生长，使得沟道区域凹陷。然后，微分氧化物生长用于掩蔽通道阈值调整和穿通植入物的源极和漏极。形成掺杂的多晶硅栅极，其中差分氧化物的较薄区域用作栅极氧化物。在所得到的结构中，穿通掺杂剂与源极和漏极间隔开，减小寄生电容并提高晶体管的切换速度。

9. 发明授权

US5783479A Structure and method for manufacturing improved FETs having T-shaped gates 失效
标题翻译：用于制造具有T形门的改进的FET的结构和方法
公开(公告)号：US5783479A
公开(公告)日：1998-07-21
申请号：US880471
申请日：1997-06-23
申请人： Horng-Chih Lin , Tiao-Yuan Huang
发明人： Horng-Chih Lin , Tiao-Yuan Huang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66515 , H01L21/28052 , H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6659
摘要： A structure and method for manufacturing improved FETs having T-shaped gates can reduce the parasitic resistance of the gate and source/drain of an FET. In the improved FETs having T-shaped gates formed according to the invention, since a buffer layer under spacers comprises a gate oxide layer and a thicker first dielectric layer, there is no stress problem as in the prior art. Furthermore, since the polysilicon gate is lower in height than the spacers, a bridge effect can be prevented. Meanwhile, since a T-shaped conductive layer is formed to increase the equivalent width of the gate, thereby avoiding the narrow line-width effect.
摘要翻译：用于制造具有T形栅极的改进的FET的结构和方法可以减小FET的栅极和源极/漏极的寄生电阻。在根据本发明形成的具有T形栅极的改进的FET中，由于垫片下面的缓冲层包括栅极氧化物层和较厚的第一介电层，所以不存在如现有技术中的应力问题。此外，由于多晶硅栅极的高度比间隔件低，所以可以防止桥接效应。同时，由于形成T形导电层以增加栅极的等效宽度，从而避免了窄的线宽效应。

10. 发明授权

US5394358A SRAM memory cell with tri-level local interconnect 失效
标题翻译：具有三级局部互连的SRAM存储单元
公开(公告)号：US5394358A
公开(公告)日：1995-02-28
申请号：US219693
申请日：1994-03-28
申请人： Tiao-Yuan Huang
发明人： Tiao-Yuan Huang
IPC分类号： H01L27/11 , G11C11/40
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A CMOS SRAM cell includes "true" and "false" NMOS word-line access transistors, "true" and "false" NMOS pull-down transistors, and "true" and "false" PMOS pull-down transistors arranged in a classical six-transistor SRAM electrical configuration. "True" and "false" inter-level interconnects of silicidable material provide for respective five-way connections among the transistors. The "true" inter-level interconnect connects: the drain of the "true" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "false" pull-up transistor and the "false" pull-down transistor, and a diffusion region defining and connecting the source of the "true" access transistor and the drain of the "true" pull-down transistor. In a complementary fashion, the "false" inter-level interconnect connects: the drain of the "false" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "true" pull-up transistor and the "true" pull-down transistor, and a diffusion region defining and connecting the drain of the "false" access transistor and the drain of the "false" pull-down transistor. These two five-way connections provide all the necessary local interconnections for the memory cell. The reduced number of inter-level local interconnects required provides for denser memory cell layouts.
摘要翻译： CMOS SRAM单元包括“真”和“假”NMOS字线存取晶体管，“真”和“假”NMOS下拉晶体管，以及布置在经典六中的“真”和“假”PMOS下拉晶体管晶体管SRAM电气配置。可硅化材料的“真”和“假”级间互连提供晶体管之间的相应的五路连接。 “真实”级间互连连接：“真”上拉晶体管的漏极，限定并连接“假”上拉晶体管的栅极和“假”（pull））下拉晶体管的栅极级多晶硅导体以及限定和连接“真”存取晶体管的源极和“真”型下拉晶体管的漏极的扩散区域。以互补的方式，“虚假”级间互连连接：“假”上拉晶体管的漏极，限定并连接“真实”上拉晶体管的栅极的栅极级多晶硅导体和“真实” “下拉晶体管”，以及限定并连接“假”存取晶体管的漏极和“假”下拉晶体管的漏极的扩散区域。这两个五路连接为存储单元提供了所有必要的局部互连。所需的层间局部互连的数量减少提供了更密集的存储单元布局。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式