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    • 8. 发明申请
    • Semiconductor memory system and signal processing system
    • 半导体存储器系统和信号处理系统
    • US20080115043A1
    • 2008-05-15
    • US11984718
    • 2007-11-21
    • Kazutoshi ShimizumeMamoru AkitaMasahiko Itoh
    • Kazutoshi ShimizumeMamoru AkitaMasahiko Itoh
    • G06F11/10
    • G06F11/1068
    • A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and/or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.
    • 一种能够加强纠错能力的半导体存储器件,能够缩短写入时间和/或读取时间,能够使冗余存储器不必要或更小,从而能够实现尺寸的减小和成本的降低, 设置有用于接收1页数据的数据输入部分,将其划分为多个码字,为每个码字生成和添加校验码(奇偶校验数据),连续形成主码字并将其传送到银行( A)或存储体(B),以及数据输出部分,用于接收包括从数据锁存电路传送的主代码字的1页数据的数据,当在每个主代码的预定数量的错误数据内存在时纠正错误数据 添加用于读取除检查码(奇偶校验数据)之外的每个读取码字的错误信息,并将其传送到主机侧,以及使用该错误信息的信号处理系统。
    • 9. 发明申请
    • Semiconductor memory device and signal processing system
    • 半导体存储器件和信号处理系统
    • US20050268208A1
    • 2005-12-01
    • US11137442
    • 2005-05-26
    • Kazutoshi ShimizumeMamoru AkitaMasahiko Itoh
    • Kazutoshi ShimizumeMamoru AkitaMasahiko Itoh
    • G11C16/02G06F11/10G11C16/06G11C29/00H03M13/00
    • G06F11/1068
    • A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and/or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data), for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.
    • 一种能够加强纠错能力的半导体存储器件,能够缩短写入时间和/或读取时间,能够使冗余存储器不必要或更小,从而能够实现尺寸的减小和成本的降低, 设置有用于接收1页数据的数据输入部分,将其划分为多个代码字,为每个代码字生成并添加校验码(奇偶校验数据),依次形成主代码字并将其传送到存储体 (A)或存储体(B),以及数据输出部分,用于接收包含从数据锁存电路传送的主代码字的1页数据的数据,当在每个主要的预定数量的错误数据内存在时,校正错误数据 添加用于读取除检查码(奇偶校验数据)之外的每个读取码字的错误信息,并将其传送到主机侧,以及使用该错误信息的信号处理系统。