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1. 发明授权

US6046469A Semiconductor storage device having a capacitor and a MOS transistor 失效
标题翻译：具有电容器和MOS晶体管的半导体存储装置
公开(公告)号：US6046469A
公开(公告)日：2000-04-04
申请号：US161483
申请日：1998-09-28
申请人： Shinobu Yamazaki , Kazuya Ishihara , Masaya Nagata
发明人： Shinobu Yamazaki , Kazuya Ishihara , Masaya Nagata
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/285 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11502 , H01L27/1085 , H01L28/75 , H01L21/28568 , H01L28/55
摘要： In a semiconductor storage device, a capacitor section is connected with a drain region of a MOS transistor by means of a polysilicon plug. The capacitor section has a lower electrode, a ferroelectric thin film, and an upper electrode stacked in this order. A TiN barrier metal is placed between the lower electrode and the plug. The lower electrode has a lower film made of a platinum-rhodium alloy and an upper film made of a platinum-rhodium alloy oxide which is in contact with the ferroelectric thin film.
摘要翻译：在半导体存储装置中，电容器部通过多晶硅插塞与MOS晶体管的漏极区域连接。电容器部具有依次层叠的下电极，铁电薄膜和上电极。在下电极和插头之间放置TiN阻挡金属。下电极具有由铂 - 铑合金制成的下膜和与铁电薄膜接触的铂 - 铑合金氧化物制成的上膜。

2. 发明授权

US06225185B1 Method for fabricating semiconductor memory having good electrical characteristics and high reliability 失效
标题翻译：具有良好的电气特性和高可靠性的半导体存储器的制造方法
公开(公告)号：US06225185B1
公开(公告)日：2001-05-01
申请号：US09427941
申请日：1999-10-27
申请人： Shinobu Yamazaki , Kazuya Ishihara
发明人： Shinobu Yamazaki , Kazuya Ishihara
IPC分类号： H01L2120
CPC分类号： H01L28/55
摘要： After forming a capacitor of a stack type ferroelectric memory device by sequentially patterning an upper electrode, a ferroelectric film and a lower electrode formed above an interlayer insulator film, the capacitor is covered with an oxidation barrier layer. After forming the oxidation barrier layer, the in-process memory device is heat treated at a high temperature in an oxygen-containing atmosphere. The oxidation barrier layer prevents the lower electrode of the capacitor and a barrier metal film between the capacitor and the interlayer insulator film from oxidation during heat treatment. Thus, the occurrence of peelings and hillocks in the lower electrode and the barrier metal film is avoided so that a semiconductor memory has good electrical characteristics and high reliability.
摘要翻译：在层叠型铁电体存储器件的电容器形成之后，通过顺序构图上层电极，铁电体膜和形成在层间绝缘膜上方的下电极，电容器被氧化阻挡层覆盖。在形成氧化阻挡层之后，在含氧气氛中在高温下热处理过程中的记忆装置。氧化阻挡层防止电容器的下电极和电容器与层间绝缘膜之间的阻挡金属膜在热处理期间氧化。因此，避免了在下电极和阻挡金属膜中产生剥离和小丘，使得半导体存储器具有良好的电特性和高可靠性。

3. 发明授权

US06232174B1 Methods for fabricating a semiconductor memory device including flattening of a capacitor dielectric film 失效
标题翻译：用于制造包括电容器电介质膜的平坦化的半导体存储器件的方法
公开(公告)号：US06232174B1
公开(公告)日：2001-05-15
申请号：US09451848
申请日：1999-12-01
申请人： Masaya Nagata , Nobuhito Ogata , Kazuya Ishihara , Jun Kudo
发明人： Masaya Nagata , Nobuhito Ogata , Kazuya Ishihara , Jun Kudo
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/31053 , H01L21/31055
摘要： In a method for fabrication a semiconductor memory device which has a capacitor having a lower electrode, a dielectric film and an upper electrode stacked in this order, after the dielectric film is formed to a desired film thickness, the dielectric film is flattened by removing the dielectric film by a specified amount. The upper electrode is formed on the flattened
摘要翻译：在制造半导体存储器件的方法中，具有具有下电极的电容器，电介质膜和上电极按此顺序堆叠，在电介质膜形成所需的膜厚之后，通过除去电介质膜而使电介质膜变平电介质膜规定量。上电极形成在平坦的上

4. 发明授权

US08422270B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08422270B2
公开(公告)日：2013-04-16
申请号：US13044892
申请日：2011-03-10
申请人： Suguru Kawabata , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
发明人： Suguru Kawabata , Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Nobuyoshi Awaya , Akio Kitagawa , Kazuya Nakayama
IPC分类号： G11C11/34
CPC分类号： G11C13/004 , G11C2013/0045 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
摘要翻译：非易失性半导体存储器件包括：位电压调整电路，对于每个位线，将选定位线和非选定位线的电位固定到预定电位以执行存储器操作，以及数据电压调整电路，每个数据线将所选数据线和未选择的数据线的电位固定到预定电位以执行存储器操作。每个电压调节电路包括运算放大器和晶体管，将存储器操作所需的电压输入到运算放大器的非反相输入端，运算放大器的反相输入端连接到位线或数据线，使得位线或数据线的电位固定为运算放大器的非反相输入端的电位。

5. 发明申请

US20120075909A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120075909A1
公开(公告)日：2012-03-29
申请号：US13212457
申请日：2011-08-18
申请人： Mitsuru NAKURA , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
发明人： Mitsuru NAKURA , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2213/32 , G11C2213/79
摘要： Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.
摘要翻译：提供一种半导体存储器件，其能够在随机存取编程动作中以期望的可控制性稳定地编程到期望的电阻状态，并且具有可变电阻元件。无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲电阻值被应用。此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。

6. 发明授权

US06538272B2 Semiconductor storage device and method of producing same 失效
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US06538272B2
公开(公告)日：2003-03-25
申请号：US09534352
申请日：2000-03-24
申请人： Shinobu Yamazaki , Kazuya Ishihara , Tetsu Miyoshi , Jun Kudo
发明人： Shinobu Yamazaki , Kazuya Ishihara , Tetsu Miyoshi , Jun Kudo
IPC分类号： H01L2976
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/3212 , H01L27/10852 , H01L28/55
摘要： A contact plug electrically connected with a MOS transistor is formed in a first interlayer dielectric. Then, a barrier metal material is deposited over the first interlayer dielectric and the contact plug, and patterned into a barrier metal electrically connected with the contact plug. After a SiN film is formed as an anti-oxygen-permeation film over the barrier metal and the first interlayer dielectric, the film is abraded by a chemical mechanical polishing technique until a top surface of the barrier metal is exposed. Then, a lower electrode material, a dielectric material and an upper electrode material are deposited in this order on the SiN film and the barrier metal, and then patterned such that a resulting lower electrode covers at least the entire upper surface of the barrier metal. Thereafter a second interlayer dielectric is deposited, and a heat treatment is performed in an oxygen ambient to recover film quality of a capacitor dielectric.
摘要翻译：在第一层间电介质中形成与MOS晶体管电连接的接触插塞。然后，将阻挡金属材料沉积在第一层间电介质和接触插塞上，并被图案化成与接触插塞电连接的阻挡金属。在阻挡金属和第一层间电介质上形成作为抗氧渗透膜的SiN膜之后，通过化学机械抛光技术对该膜进行研磨，直至暴露出阻挡金属的顶表面。然后，在SiN膜和阻挡金属上依次沉积下电极材料，电介质材料和上电极材料，然后图案化，使得所得的下电极至少覆盖阻挡金属的整个上表面。此后，沉积第二层间电介质，并在氧环境中进行热处理以恢复电容器电介质的膜质量。

7. 发明授权

US08514607B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08514607B2
公开(公告)日：2013-08-20
申请号：US13212457
申请日：2011-08-18
申请人： Mitsuru Nakura , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
发明人： Mitsuru Nakura , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2213/32 , G11C2213/79
摘要： Provided is a semiconductor memory device that is capable of stably programming with desirable controllability to a desired electric resistance state in a random access programming action and is provided with a variable resistance element. Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided.
摘要翻译：提供一种半导体存储器件，其能够在随机存取编程动作中以期望的可控制性稳定地编程到期望的电阻状态，并且具有可变电阻元件。无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲电阻值被应用。此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。

8. 发明授权

US08482956B2 Semiconductor memory device and method of driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08482956B2
公开(公告)日：2013-07-09
申请号：US13179839
申请日：2011-07-11
申请人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
发明人： Shinobu Yamazaki , Yoshiji Ohta , Kazuya Ishihara , Mitsuru Nakura , Suguru Kawabata , Nobuyoshi Awaya
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： A semiconductor memory device includes a memory cell array where a plurality of memory cells are arranged in a matrix, each of the memory cells serially connecting a two-terminal type memory element and a transistor for selection, a first voltage applying circuit that applies a write voltage pulse to a bit line, and a second voltage applying circuit that applies a precharge voltage to a bit line and a common line. In writing the memory cell, after the second voltage applying circuit has both terminals of the memory cell previously precharged to the same voltage, the first voltage applying circuit applies the write voltage pulse to one terminal of the writing target memory cell via the bit line, and while the write voltage pulse is applied, the second voltage applying circuit maintains the application of the precharge voltage to the other terminal of the memory cell via the common line.
摘要翻译：半导体存储器件包括：存储单元阵列，其中多个存储单元以矩阵形式布置，每个存储单元串联连接两端型存储元件和晶体管供选择;第一施加电压电路，电压脉冲到位线，以及第二电压施加电路，其向位线和公共线施加预充电电压。在写入存储单元时，在第二电压施加电路具有先前预充电至相同电压的存储单元的两端，第一电压施加电路经由位线将写入电压脉冲施加到写入目标存储单元的一个端子，并且当施加写入电压脉冲时，第二电压施加电路通过公共线路将预充电电压保持到存储单元的另一个端子。

9. 发明授权

US08411487B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08411487B2
公开(公告)日：2013-04-02
申请号：US13224814
申请日：2011-09-02
申请人： Mitsuru Nakura , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
发明人： Mitsuru Nakura , Kazuya Ishihara , Shinobu Yamazaki , Suguru Kawabata
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097
摘要： Regardless of a resistance state of a variable resistance element of a memory cell that is a target of a writing action (erasing and programming actions), an erasing voltage pulse for bringing the resistance state of the variable resistance element to an erased state having a lowest resistance value is applied. Thereafter, a programming voltage pulse for bringing the resistance state of the variable resistance element to a desired programmed state is applied to the variable resistance element of the programming action target memory cell. By always applying the programming voltage pulse after having applied the erasing voltage pulse, a plurality of programming voltage pulses being sequentially applied can be avoided. Further, the memory cell array is constituted of even-numbers of subbanks, and the application of the erasing voltage pulse in one subbank and the application of the programming voltage pulse in the other subbank are alternately performed.
摘要翻译：无论作为写入动作（擦除和编程动作）的目标的存储单元的可变电阻元件的电阻状态，将可变电阻元件的电阻状态变为最低的擦除状态的擦除电压脉冲电阻值被应用。此后，将用于使可变电阻元件的电阻状态变为期望编程状态的编程电压脉冲被施加到编程动作目标存储单元的可变电阻元件。通过在施加擦除电压脉冲之后始终应用编程电压脉冲，可以避免顺序施加的多个编程电压脉冲。此外，存储单元阵列由偶数个子库构成，并且将擦除电压脉冲应用于一个子库中，并且编程电压脉冲在另一个子库中的应用被交替执行。

10. 发明申请

US20120300532A1 METHOD OF FORMING PROCESS FOR VARIABLE RESISTIVE ELEMENT AND NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：可变电阻元件和非易失性半导体存储器件的形成方法
公开(公告)号：US20120300532A1
公开(公告)日：2012-11-29
申请号：US13478498
申请日：2012-05-23
申请人： Shinobu Yamazaki , Kazuya Ishihara , Suguru Kawabata
发明人： Shinobu Yamazaki , Kazuya Ishihara , Suguru Kawabata
IPC分类号： G11C11/21 , H01L21/02
CPC分类号： G11C13/0069 , G11C11/16 , G11C13/0007 , G11C2013/0083 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , H01L27/2436 , H01L45/08 , H01L45/1226 , H01L45/1266 , H01L45/146
摘要： A method of a forming process for a variable resistive element, which is performed in short time comparable to the pulse forming and a writing current in a switching action is the same level as that of the DC forming, is provided. In the forming process, a variable resistive element is changed by voltage pulse application from an initial high resistance state just after produced to a variable resistance state where the switching action is performed. The forming process includes a first step of applying a first pulse having a voltage amplitude lower than a threshold voltage at which the resistance of the variable resistive element is lowered, to between both electrodes of the variable resistive element, and a second step of applying a second pulse having a voltage amplitude having the same polarity as the first pulse and not lower than the threshold voltage, thereto after the first step.
摘要翻译：提供了一种与可变电阻元件的形成处理方法相比，其在与开关动作中的脉冲形成和写入电流相当的短时间内进行，与DC形成相同。在形成过程中，可变电阻元件由刚刚产生的初始高电阻状态的电压脉冲施加到执行开关动作的可变电阻状态而改变。该形成工艺包括将可变电阻元件的电阻降低的电压幅度低于阈值电压的第一脉冲施加到可变电阻元件的两个电极之间的第一步骤，在第一步骤之后具有与第一脉冲具有相同极性且不低于阈值电压的电压振幅的第二脉冲。

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