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1. 发明授权

US08503259B2 Memory test method and memory test device 有权
标题翻译：内存测试方法和内存测试设备
公开(公告)号：US08503259B2
公开(公告)日：2013-08-06
申请号：US12382485
申请日：2009-03-17
申请人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
发明人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C2029/3602
摘要： A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
摘要翻译：通过顺序地生成多个n位地址来执行存储器测试，其中第一到第k位（1 @ k @ n）都被设置为两个值0或1中的一个，并且其（k + 1）对于从1到n的所有k，所有第th到第n位都被设置为两个值中的另一个值; 将第一测试数据写入存储器中的每个生成的地址; 从存储器中的每个地址读取第二测试数据; 以及将所述第一测试数据与所述第二测试数据进行比较。

2. 发明授权

US08143901B2 Test apparatus, test method, and integrated circuit 失效
标题翻译：测试仪器，测试方法和集成电路
公开(公告)号：US08143901B2
公开(公告)日：2012-03-27
申请号：US12379371
申请日：2009-02-19
申请人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
发明人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
IPC分类号： G01R31/02
CPC分类号： G11C29/20 , G11C29/56004 , G11C2029/3602
摘要： A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.
摘要翻译：测试装置包括一个向上计数器，一个递减计数器，一个选择器，其选择从递增计数器输出的上升计数器或从递减计数器输出的递减计数器;反相电路，反相由选择器选择的计数器输出或由选择器选择的计数器输出，以及比较电路，其比较由反相电路反相的计数器输出和另一个计数器输出。

3. 发明申请

US20090300443A1 Test apparatus, test method, and integrated circuit 失效
标题翻译：测试仪器，测试方法和集成电路
公开(公告)号：US20090300443A1
公开(公告)日：2009-12-03
申请号：US12379371
申请日：2009-02-19
申请人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
发明人： Chikahiro Deguchi , Yutaka Sekino , Shogo Shibazaki , Shinkichi Gama , Takeshi Nagase , Hideyuki Negi
IPC分类号： G06F11/22
CPC分类号： G11C29/20 , G11C29/56004 , G11C2029/3602
摘要： A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.
摘要翻译：测试装置包括一个向上计数器，一个递减计数器，一个选择器，其选择从递增计数器输出的上升计数器或从递减计数器输出的递减计数器;反相电路，反相由选择器选择的计数器输出或由选择器选择的计数器输出，以及比较电路，其比较由反相电路反相的计数器输出和另一个计数器输出。

4. 发明申请

US20070165864A1 Encryption device 有权
标题翻译：加密设备
公开(公告)号：US20070165864A1
公开(公告)日：2007-07-19
申请号：US11312611
申请日：2005-12-21
申请人： Takeshi Nagase , Shogo Shibazaki , Shinkichi Gama
发明人： Takeshi Nagase , Shogo Shibazaki , Shinkichi Gama
IPC分类号： H04L9/00
CPC分类号： G06F21/85 , G06F21/602 , G06F21/78
摘要： An encryption/decryption processing unit performs encryption/decryption processing of data transmitted from a host system, and encryption/decryption processing of key data used for encryption/decryption of the data. A key data buffer temporarily stores encrypted key data. A key data buffer temporarily stores unencrypted key data. An external memory interface controls flash memory attached outside, and reads/writes encrypted key data stored in the key data buffer.
摘要翻译：加密/解密处理单元执行从主机系统发送的数据的加密/解密处理以及用于数据的加密/解密的密钥数据的加密/解密处理。密钥数据缓冲器临时存储加密的密钥数据。密钥数据缓冲区临时存储未加密的密钥数据。外部存储器接口控制外部附加的闪存，并读取/写入存储在密钥数据缓冲器中的加密密钥数据。

5. 发明授权

US07076667B1 Storage device having secure test process 失效
标题翻译：存储设备具有安全的测试过程
公开(公告)号：US07076667B1
公开(公告)日：2006-07-11
申请号：US09531105
申请日：2000-03-17
申请人： Shinkichi Gama , Shogo Shibazaki
发明人： Shinkichi Gama , Shogo Shibazaki
IPC分类号： G06F12/14
CPC分类号： G11C29/46 , G01R31/31719 , G11C16/04
摘要： In a storage device for maintaining information when power is OFF and being capable of executing a test process based on test signals, a test terminal inputs the test signals and an instruction part sends a read out instruction for instructing a memory storing secret data to read out data. Moreover, a decoding part decodes whether or not the data read out by the memory in response to the data reading instruction is the secret data stored in the memory and a maintaining part maintains information in a volatile state resulting from the decoding part. Furthermore, a cutting-off part cuts off the test signals input from the test terminal when the maintaining part maintains information indicating that the secret data is stored.
摘要翻译：在用于在断电时维持信息并且能够基于测试信号执行测试处理的存储设备中，测试终端输入测试信号，并且指令部分发送读出指令，用于指示存储秘密数据的存储器读出数据。此外，解码部分解码响应于数据读取指令由存储器读出的数据是否是存储在存储器中的秘密数据，并且维护部分维持由解码部分产生的易失性状态的信息。此外，当维护部保持指示秘密数据被存储的信息时，切断部分切断从测试终端输入的测试信号。

6. 发明授权

US07689836B2 Encryption device 有权
标题翻译：加密设备
公开(公告)号：US07689836B2
公开(公告)日：2010-03-30
申请号：US11312611
申请日：2005-12-21
申请人： Takeshi Nagase , Shogo Shibazaki , Shinkichi Gama
发明人： Takeshi Nagase , Shogo Shibazaki , Shinkichi Gama
IPC分类号： H04L9/32 , H04L9/00
CPC分类号： G06F21/85 , G06F21/602 , G06F21/78
摘要： An encryption/decryption processing unit performs encryption/decryption processing of data transmitted from a host system, and encryption/decryption processing of key data used for encryption/decryption of the data. A key data buffer temporarily stores encrypted key data. A key data buffer temporarily stores unencrypted key data. An external memory interface controls flash memory attached outside, and reads/writes encrypted key data stored in the key data buffer.
摘要翻译：加密/解密处理单元执行从主机系统发送的数据的加密/解密处理以及用于数据的加密/解密的密钥数据的加密/解密处理。密钥数据缓冲器临时存储加密的密钥数据。密钥数据缓冲区临时存储未加密的密钥数据。外部存储器接口控制外部附加的闪存，并读取/写入存储在密钥数据缓冲器中的加密密钥数据。

7. 发明申请

US20090296505A1 Memory test method and memory test device 有权
标题翻译：内存测试方法和内存测试设备
公开(公告)号：US20090296505A1
公开(公告)日：2009-12-03
申请号：US12382485
申请日：2009-03-17
申请人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
发明人： Shogo Shibazaki , Shinkichi Gama , Hideyuki Negi , Takeshi Nagase , Chikahiro Deguchi , Yutaka Sekino
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C2029/3602
摘要： A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
摘要翻译：通过顺序地生成多个n位地址来执行存储器测试，其中第一至第k位（1 <= k <= n）都被设置为两个值0或1之一，并且其（k + 对于从1到n的所有k，所有1到第n位都被设置为两个值中的另一个值; 将第一测试数据写入存储器中的每个生成的地址; 从存储器中的每个地址读取第二测试数据; 以及将所述第一测试数据与所述第二测试数据进行比较。

8. 发明授权

US06125424A Method of writing, erasing, and controlling memory and memory device having erasing and moving components 失效
标题翻译：写入，擦除和控制具有擦除和移动部件的存储器和存储器件的方法
公开(公告)号：US06125424A
公开(公告)日：2000-09-26
申请号：US10795
申请日：1998-01-22
申请人： Shinpei Komatsu , Yumi Ishii , Tomohiro Hayashi , Shogo Shibazaki , Hiroyuki Itoh , Masaru Takehara
发明人： Shinpei Komatsu , Yumi Ishii , Tomohiro Hayashi , Shogo Shibazaki , Hiroyuki Itoh , Masaru Takehara
IPC分类号： G11C16/02 , G06F12/00 , G06F12/02 , G11C16/06 , G11C29/00 , G11C29/04 , G06F13/00
CPC分类号： G11C29/765 , G11C29/76 , G11C29/82
摘要： Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.
摘要翻译：从主计算机传送到存储器件的数据被写入到存储器区域中的地址由解码表解码的扇区。由上述数据更新的旧数据将被擦除或标记为擦除标志。在预定的时间点，为了创建空闲区域，将必要的数据撤回到主存储介质，并且通过预定存储器大小的单位擦除由擦除标志指示的不必要的数据。存在缺陷的存储介质的一部分标有缺陷标志，并被备用区域代替。在这样做时，解码表被重写以重新排列存储器区域。

9. 发明授权

US06625712B2 Memory management table producing method and memory device 有权
标题翻译：内存管理表生成方法和存储器件
公开(公告)号：US06625712B2
公开(公告)日：2003-09-23
申请号：US09801671
申请日：2001-03-09
申请人： Shogo Shibazaki , Takeshi Nagase
发明人： Shogo Shibazaki , Takeshi Nagase
IPC分类号： G06F1200
CPC分类号： G06F12/02
摘要： The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information of memory areas which are data storage destinations designated by a logical address issued by a host device. After an initializing process, the host device is immediately notified of canceling of a busy state, without production of the memory management table. Alternatively, only a part of the memory management table is produced and the host device is notified of the canceling of the busy state. After that, until the host device issues a process request, or when the host device is issuing a process request, an incomplete part of the memory management table is completed. Thus, the memory management table can be completed.
摘要翻译：本发明涉及一种制造存储器管理表的方法，该存储器管理表控制具有在断电时保持数据的功能的存储器，并且管理存储区域的标识符信息，所述存储器区域是由逻辑地址发出的逻辑地址指定的数据存储目的地主机设备。在初始化处理之后，主机设备立即被通知取消繁忙状态，而不产生存储器管理表。或者，仅产生存储器管理表的一部分，并且向主机设备通知取消忙碌状态。之后，直到主机设备发出处理请求，或当主机设备发出处理请求时，完成了内存管理表的不完整部分。因此，可以完成存储器管理表。

10. 发明授权

US6118312A Clock switch circuit 有权
标题翻译：时钟开关电路
公开(公告)号：US6118312A
公开(公告)日：2000-09-12
申请号：US281231
申请日：1999-03-30
申请人： Shogo Shibazaki
发明人： Shogo Shibazaki
IPC分类号： G06F1/06 , G06F1/08 , H03K5/00 , H03B19/00
CPC分类号： H03K5/00006 , G06F1/08
摘要： A clock circuit which selectively outputs a clock signal of a frequency equal to an integer multiple of a frequency of a master clock signal includes a setting circuit which sets a value corresponding to a target frequency of the clock signal, a counting circuit which counts pulses of the master clock signal, and an extracting circuit which extracts a pulse of the master clock signal each time a counter value of the counting circuit becomes equal to the value set by the setting circuit.
摘要翻译：选择性地输出等于主时钟信号的频率的整数倍的时钟信号的时钟电路包括设定电路，其设定与时钟信号的目标频率对应的值，计数电路对主时钟信号，以及每当计数电路的计数器值等于由设置电路设置的值时提取主时钟信号的脉冲的提取电路。

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