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    • 4. 发明授权
    • Ferroelectric memory with disturb protection
    • 铁电存储器具有干扰保护
    • US6151241A
    • 2000-11-21
    • US314800
    • 1999-05-19
    • Shinichiro HayashiTatsuo OtsukiCarlos A. Paz de Araujo
    • Shinichiro HayashiTatsuo OtsukiCarlos A. Paz de Araujo
    • G11C11/22H01L21/336H01L29/51G11C11/00
    • H01L29/6684G11C11/22H01L29/516
    • A ferroelectric field effect transistor memory cell includes a thin film varistor located between the gate electrode and the ferroelectric layer. The varistor protects the ferroelectric layer from disturb voltage pulses arising from memory read, write and sense operations. A second electrode is located between the thin film varistor and the ferroelectric layer. The thin film ferroelectric is positioned over the channel of a transistor to operate as a ferroelectric gate. For voltages at which disturb voltages are likely to occur, the thin film varistor has a resistance obeying a formula R.sub.d >10.times.1/(2.pi.fC.sub.F), where R.sub.d is resistivity of the thin film varistor, f is an operating frequency of said memory, and C.sub.F is the capacitance of the ferroelectric layer. For voltages at or near the read and write voltage of the memory, the thin film varistor has a resistance obeying a formula R.sub.d
    • 铁电场效应晶体管存储单元包括位于栅电极和铁电层之间的薄膜变阻器。 压敏电阻保护铁电层不受存储器读,写和读操作引起的干扰电压脉冲的影响。 第二电极位于薄膜压敏电阻和铁电层之间。 薄膜铁电体位于晶体管的沟道上方,用作铁电栅极。 对于可能发生干扰电压的电压,薄膜压敏电阻具有遵循公式Rd> 10×1 /(2πfCF)的电阻,其中Rd是薄膜变阻器的电阻率,f是所述存储器的工作频率, CF是铁电层的电容。 对于等于或接近存储器的读和写电压的电压,薄膜压敏电阻具有遵循公式Rd <0.1x1 /(2πfCF)的电阻。