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1. 发明授权

US5949486A Unit for detecting motion vector for motion compensation 失效
标题翻译：用于检测运动补偿运动矢量的单元
公开(公告)号：US5949486A
公开(公告)日：1999-09-07
申请号：US795217
申请日：1997-02-05
申请人： Kazuya Ishihara , Shinichi Uramoto , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami , Shinichi Masuda
发明人： Kazuya Ishihara , Shinichi Uramoto , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami , Shinichi Masuda
IPC分类号： H04N19/50 , H03M7/30 , H03M7/36 , H04N5/14 , H04N19/423 , H04N19/436 , H04N19/51 , H04N7/12
CPC分类号： H04N19/433 , H04N19/51 , H04N5/145
摘要： Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.
摘要翻译：与模板块和搜索窗口块的像素相对应地布置的每个元素处理器分别包括彼此并行提供的用于存储搜索窗口块像素数据的A寄存器和B寄存器，以及用于存储模板块的T寄存器像素数据。通过A和B寄存器中的第一个和存储在T寄存器中的像素数据执行运动矢量评估值计算，而操作数据从A和B中的第一个传送到A和B寄存器中的第二个， B与计算操作并行登记，用于存储下一个搜索窗口的头部搜索窗口块像素数据。以良好的编码效率高速检测运动矢量。

2. 发明授权

US5732249A Clock distributing circuit 失效
标题翻译：时钟分配电路
公开(公告)号：US5732249A
公开(公告)日：1998-03-24
申请号：US578432
申请日：1995-12-26
申请人： Shinichi Masuda , Kazuya Ishihara
发明人： Shinichi Masuda , Kazuya Ishihara
IPC分类号： G06F1/10 , H03K5/15 , H03K19/0175 , G06F1/04
CPC分类号： G06F1/10
摘要： To improve the clock delay time and skew. A first resistance body (R1) and a second resistance body (R2) are provided at a terminal end node (N5) of a clock trunk line (1) composed of a doped polysilicon film or the like. Their elements (R1), (R2) are composed of the same film as the clock trunk line (1). Their resistance ratio is set so that the clamp level may be an inverted threshold of first and second local drivers (D2, D3), and the resistance values of both resistance bodies (R1, R2), and the value of interconnection resistance (R) of the clock trunk line (1) are set so that an amplitude of a clock signal at each of the nodes (N3, N4, N5) may be a potential corresponding to 1/2 of its peak-to-peak voltage at the same time. The amplitude of the clock signal from a start end node (N3) to a terminal end node (N5) decreases, and the delay time from an output of a clock driver (D1) to outputs of the local drivers (D2, D3) shaped in waveform is much shorter, and hence the clock skew of the outputs hardly occurs.
摘要翻译：提高时钟延迟时间和偏移。在由掺杂多晶硅膜等构成的时钟主干线（1）的终端节点（N5）上设置有第一电阻体（R1）和第二电阻体（R2）。它们的元件（R1），（R2）由与时钟主干线（1）相同的膜组成。设置它们的电阻比，使得钳位电平可以是第一和第二局部驱动器（D2，D3）的反相阈值，并且两个电阻体（R1，R2）的电阻值和互连电阻值（R）时钟中继线（1）的时钟信号的幅度被设置为使得每个节点（N3，N4，N5）处的时钟信号的幅度可以是对应于+ E的电位，其峰值的频率为1/2 + EE -peak电压同时。从起始端节点（N3）到终端节点（N5）的时钟信号的幅度减小，并且从时钟驱动器（D1）的输出到本地驱动器（D2，D3）的输出的延迟时间成形波形较短，因此几乎不发生输出的时钟偏移。

3. 发明授权

US08645795B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08645795B2
公开(公告)日：2014-02-04
申请号：US13462846
申请日：2012-05-03
申请人： Kazuya Ishihara , Yoshiaki Tabuchi
发明人： Kazuya Ishihara , Yoshiaki Tabuchi
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G06F11/1048 , G11C13/0002 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2029/0411
摘要： The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.
摘要翻译：本发明提供一种能够优化执行错误检测和校正处理的定时以缩短处理时间的非易失性半导体存储器件。一旦输入/输出缓冲器向写入控制单元和ECC控制单元输出写入数据，就向存储单元阵列接收到写入请求，该存储单元阵列包括基于可变电阻器的电阻状态存储信息的可变电阻元件。写入控制单元执行写入分割数据的数据写入处理，该分割数据是通过将写入数据划分成预定数量的数据而获得的。 ECC控制单元通过与数据写入处理并行地对写入数据或分割数据执行纠错码生成处理来生成第一纠错码。写入控制单元执行将第一测试数据写入ECC组的代码写入处理。

4. 发明授权

US08115586B2 Variable resistance element, and its manufacturing method 有权
标题翻译：可变电阻元件及其制造方法
公开(公告)号：US08115586B2
公开(公告)日：2012-02-14
申请号：US12298089
申请日：2007-02-16
申请人： Yasunari Hosoi , Kazuya Ishihara , Takahiro Shibuya , Tetsuya Ohnishi , Takashi Nakano
发明人： Yasunari Hosoi , Kazuya Ishihara , Takahiro Shibuya , Tetsuya Ohnishi , Takashi Nakano
IPC分类号： H01C7/10 , H01C7/13
CPC分类号： H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1633 , H01L45/1691 , Y10T29/49082
摘要： Provided are a variable resistive element having a configuration that the area of an electrically contributing region in a variable resistor body is smaller than the area defined by an upper electrode or a lower electrode, and a method for manufacturing the variable resistive element. The cross section of a current path, in which an electric current flows through between the two electrodes via the variable resistor body at the time of applying the voltage pulse to between the two electrodes, is formed with a line width of narrower than that of any of the two electrodes and of smaller than a minimum work dimension regarding manufacturing processes, so that its area can be made smaller than that of the electrically contributing region in the variable resistive element of the prior art.
摘要翻译：提供了一种可变电阻元件，其具有可变电阻体中的电赋值区域小于由上电极或下电极限定的面积的构造，以及制造可变电阻元件的方法。在将电压脉冲施加到两个电极之间时，通过可变电阻体在两个电极之间流过电流的电流路径的横截面形成为比任何电极的线宽窄的线宽并且小于关于制造工艺的最小工作尺寸，使得其面积可以比现有技术的可变电阻元件中的电赋值区的面积小。

5. 发明授权

US08115585B2 Variable resistance element 有权
标题翻译：可变电阻元件
公开(公告)号：US08115585B2
公开(公告)日：2012-02-14
申请号：US11994646
申请日：2006-07-05
申请人： Kazuya Ishihara
发明人： Kazuya Ishihara
IPC分类号： H01C7/10
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/52 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1683
摘要： In a variable resistance element having a variable resistor between first and second electrodes and changing its electric resistance when a voltage pulse is applied between both electrodes, data holding characteristics can be improved by increasing a programming voltage and programming in a high current density. Therefore, a booster circuit for supplying a high voltage is needed when the variable resistance element is applied to a nonvolatile memory. When the smaller of the areas of the contact regions between the first electrode and variable resistor and between the second electrode and variable resistor is set to the electrode area of the variable resistance element, it is set within a specific range not larger than the predetermined electrode area. Thereby the programming current density can be increased without raising the programming voltage, and the variable resistance element having preferable data holding characteristics even at a high temperature can be provided.
摘要翻译：在具有第一和第二电极之间的可变电阻器的可变电阻元件中，并且当在两个电极之间施加电压脉冲时改变其电阻，可以通过增加编程电压并以高电流密度编程来提高数据保持特性。因此，当可变电阻元件被施加到非易失性存储器时，需要用于提供高电压的升压电路。当第一电极和可变电阻器之间以及第二电极和可变电阻器之间的接触区域中较小的区域被设置为可变电阻元件的电极区域时，其设定在不大于预定电极的特定范围内区。因此，可以提高编程电流密度而不提高编程电压，并且可以提供即使在高温也具有优选数据保持特性的可变电阻元件。

6. 发明授权

US07894239B2 Variable resistance element, method for producing the same, and nonvolatile semiconductor storage device 有权
标题翻译：可变电阻元件及其制造方法以及非易失性半导体存储器件
公开(公告)号：US07894239B2
公开(公告)日：2011-02-22
申请号：US12328648
申请日：2008-12-04
申请人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Fumiyoshi Takano , Hiroyuki Akinaga
发明人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Fumiyoshi Takano , Hiroyuki Akinaga
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C13/0007 , G11C13/0028 , G11C2013/0083 , G11C2213/32 , G11C2213/56 , G11C2213/77 , H01C7/108 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1658 , Y10T29/49082
摘要： The variable resistance element of the present invention is a variable resistance element having an electrode, the other electrode, and a metal oxide material sandwiched between the electrodes and having an electrical resistance, between the electrodes, changing reversibly in response to a voltage applied between the electrodes. The variable resistance element further includes, inside the metal oxide material, a low resistance material having a lower electrical resistance than the metal oxide material and being out of contact with at least either one of the electrodes. This makes it possible to reduce a forming voltage for providing a conductive section inside the metal oxide material, without causing a leakage current to increase.
摘要翻译：本发明的可变电阻元件是具有电极，另一个电极和夹在电极之间并具有电阻的金属氧化物材料的可变电阻元件，在电极之间，响应于施加在电极之间的电压而可逆地改变电极。可变电阻元件还包括在金属氧化物材料内部的具有比金属氧化物材料低的电阻并且与至少任一个电极不接触的低电阻材料。这使得可以降低用于在金属氧化物材料内部提供导电部分的形成电压，而不会导致泄漏电流增加。

7. 发明申请

US20090147558A1 VARIABLE RESISTANCE ELEMENT, METHOD FOR PRODUCING THE SAME, AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：可变电阻元件，其制造方法和非易失性半导体存储器件
公开(公告)号：US20090147558A1
公开(公告)日：2009-06-11
申请号：US12328648
申请日：2008-12-04
申请人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Fumiyoshi Takano , Hiroyuki Akinaga
发明人： Yukio Tamai , Yasunari Hosoi , Nobuyoshi Awaya , Shigeo Ohnishi , Kazuya Ishihara , Hisashi Shima , Fumiyoshi Takano , Hiroyuki Akinaga
IPC分类号： G11C11/21 , H01C7/10 , H01C17/00
CPC分类号： G11C8/08 , G11C13/0007 , G11C13/0028 , G11C2013/0083 , G11C2213/32 , G11C2213/56 , G11C2213/77 , H01C7/108 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1658 , Y10T29/49082
摘要： The variable resistance element of the present invention is a variable resistance element having an electrode, the other electrode, and a metal oxide material sandwiched between the electrodes and having an electrical resistance, between the electrodes, changing reversibly in response to a voltage applied between the electrodes. The variable resistance element further includes, inside the metal oxide material, a low resistance material having a lower electrical resistance than the metal oxide material and being out of contact with at least either one of the electrodes. This makes it possible to reduce a forming voltage for providing a conductive section inside the metal oxide material, without causing a leakage current to increase.
摘要翻译：本发明的可变电阻元件是具有电极，另一个电极和夹在电极之间并具有电阻的金属氧化物材料的可变电阻元件，在电极之间，响应于施加在电极之间的电压而可逆地改变电极。可变电阻元件还包括在金属氧化物材料内部的具有比金属氧化物材料低的电阻并且与至少任一个电极不接触的低电阻材料。这使得可以降低用于在金属氧化物材料内部提供导电部分的形成电压，而不会导致泄漏电流增加。

8. 发明申请

US20080169569A1 Bonding pad of semiconductor integrated circuit, method for manufacturing the bonding pad, semiconductor integrated circuit, and electronic device 审中-公开
标题翻译：半导体集成电路的接合焊盘，用于制造接合焊盘的方法，半导体集成电路和电子器件
公开(公告)号：US20080169569A1
公开(公告)日：2008-07-17
申请号：US12003718
申请日：2007-12-31
申请人： Kazuya Ishihara , Nobuyoshi Awaya
发明人： Kazuya Ishihara , Nobuyoshi Awaya
IPC分类号： H01L23/488
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/451 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/05042 , H01L2924/14 , H01L2224/48 , H01L2224/05552
摘要： According to the present invention, a bonding pad 10 of a semiconductor integrated circuit is arranged such that the opening pathways P through which metal wiring layers are connected have openings of at least two different widths including: a first width required to fill the opening pathway; and a second width being larger than the first width, and the openings are arranged lengthwise and crosswise.
摘要翻译：根据本发明，半导体集成电路的接合焊盘10被布置成使得金属布线层连接的开口通路P具有至少两个不同宽度的开口，包括：填充开口路径所需的第一宽度; 并且第二宽度大于第一宽度，并且开口纵向和横向设置。

9. 发明授权

US06919593B2 Semiconductor memory device and method of fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06919593B2
公开(公告)日：2005-07-19
申请号：US10213374
申请日：2002-08-07
申请人： Kazuya Ishihara
发明人： Kazuya Ishihara
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L27/115 , H01L27/108
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： A ferroelectric capacitor having a ferroelectric film is formed on a conductive silicon substrate. The dielectric capacitor is covered with a first diffusion barrier film, and a second interlayer insulating film is formed on the first diffusion barrier film. A first metal wiring is formed on the second interlayer insulating film, and the first metal wiring is covered with a first buffer film. A second diffusion barrier film is formed on the first buffer film, and a third interlayer insulating film is formed on the second diffusion barrier film. A second metal wiring is formed on the third interlayer insulating film, and the second metal wiring is covered with a second buffer film. A third diffusion barrier film is formed on the second buffer film.
摘要翻译：在导电硅衬底上形成具有铁电体膜的铁电电容器。介电电容器被第一扩散阻挡膜覆盖，在第一扩散阻挡膜上形成第二层间绝缘膜。在第二层间绝缘膜上形成第一金属布线，第一金属布线被第一缓冲膜覆盖。在第一缓冲膜上形成第二扩散阻挡膜，在第二扩散阻挡膜上形成第三层间绝缘膜。在第三层间绝缘膜上形成第二金属布线，第二金属布线被第二缓冲膜覆盖。在第二缓冲膜上形成第三扩散阻挡膜。

10. 发明授权

US06687303B1 Motion vector detecting device 失效
标题翻译：运动矢量检测装置
公开(公告)号：US06687303B1
公开(公告)日：2004-02-03
申请号：US09420572
申请日：1999-10-19
申请人： Kazuya Ishihara
发明人： Kazuya Ishihara
IPC分类号： H04N712
CPC分类号： H04N5/145 , H04N19/112 , H04N19/43 , H04N19/523
摘要： Data transfer paths between shift registers arranged corresponding to element processors and delay buffers arranged corresponding to shift register columns are changed in accordance with sub-sampling rate information. The delay buffer and the shift register column transfer the search window block pixel data. The element processor stores the template block pixel data. Motion vectors can be detected fast with high accuracy without increase of a volume of hardware.
摘要翻译：根据子采样率信息改变对应于元件处理器布置的移位寄存器和对应于移位寄存器列排列的延迟缓冲器之间的数据传输路径。延迟缓冲器和移位寄存器列传送搜索窗口块像素数据。元素处理器存储模板块像素数据。可以高精度地快速检测运动矢量，而不会增加硬件的体积。

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