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1. 发明授权

US08041850B2 Storage apparatus and data integrity assurance method 有权
标题翻译：存储设备和数据完整性保证方法
公开(公告)号：US08041850B2
公开(公告)日：2011-10-18
申请号：US12310670
申请日：2009-02-19
申请人： Shinichi Kasahara , Osamu Torigoe , Tetsuya Kojima , Takeshi Ishiguro
发明人： Shinichi Kasahara , Osamu Torigoe , Tetsuya Kojima , Takeshi Ishiguro
IPC分类号： G06F3/00 , G06F13/28 , G06F13/38 , G06F5/00
CPC分类号： G06F11/1076 , G06F2211/1009
摘要： A channel control unit of a storage apparatus is provided with: a variable-length DMA (Direct Memory Access) that performs data transfer of variable-length data sent to or received from the host computer in accordance with an I/O request; a fixed-length DMA that performs data transfer of fixed-length data to and from the cache memory; and a buffer intervening between the variable-length DMA and the fixed-length DMA. In performing the data transfer of the fixed-length data to the cache memory, the fixed-length DMA divides the variable-length data into multiple sets of the fixed-length data each having a data size equivalent to a unit size of data managed in the cache memory, and adds a first integrity code to the last fixed-length data set of the fixed-length data sets generated by the division, the first integrity code being generated based on the entire variable-length data.
摘要翻译：存储装置的信道控制单元具有：可变长度DMA（直接存储器访问），其根据I / O请求执行向主机发送或从其接收的可变长度数据的数据传输; 一个固定长度的DMA，用于执行固定长度数据到和从高速缓冲存储器的数据传输; 以及介于可变长度DMA和固定长度DMA之间的缓冲器。在将固定长度数据的数据传输执行到高速缓冲存储器时，固定长度的DMA将可变长度数据划分为多组固定长度数据，每组固定长度数据具有与管理的数据的单位大小相等的数据大小高速缓存存储器，并且将第一完整性代码添加到由分割生成的固定长度数据集的最后固定长度数据集合中，基于整个可变长度数据生成第一完整性代码。

2. 发明申请

US20100211703A1 Storage Apparatus and Data Integrity Assurance Method 有权
标题翻译：存储设备和数据完整性保证方法
公开(公告)号：US20100211703A1
公开(公告)日：2010-08-19
申请号：US12310670
申请日：2009-02-19
申请人： Shinichi Kasahara , Osamu Torigoe
发明人： Shinichi Kasahara , Osamu Torigoe
IPC分类号： G06F13/28 , G06F12/00 , G06F12/08
CPC分类号： G06F11/1076 , G06F2211/1009
摘要： A channel control unit of a storage apparatus is provided with: a variable-length DMA (Direct Memory Access) that performs data transfer of variable-length data sent to or received from the host computer in accordance with an I/O request; a fixed-length DMA that performs data transfer of fixed-length data to and from the cache memory; and a buffer intervening between the variable-length DMA and the fixed-length DMA. In performing the data transfer of the fixed-length data to the cache memory, the fixed-length DMA divides the variable-length data into multiple sets of the fixed-length data each having a data size equivalent to a unit size of data managed in the cache memory, and adds a first integrity code to the last fixed-length data set of the fixed-length data sets generated by the division, the first integrity code being generated based on the entire variable-length data.
摘要翻译：存储装置的信道控制单元具有：可变长度DMA（直接存储器访问），其根据I / O请求执行向主机发送或从其接收的可变长度数据的数据传输; 一个固定长度的DMA，用于执行固定长度数据到和从高速缓冲存储器的数据传输; 以及介于可变长度DMA和固定长度DMA之间的缓冲器。在将固定长度数据的数据传输执行到高速缓冲存储器时，固定长度的DMA将可变长度数据划分为多组固定长度数据，每组固定长度数据具有与管理的数据的单位大小相等的数据大小高速缓存存储器，并且将第一完整性代码添加到由分割生成的固定长度数据集的最后固定长度数据集合中，基于整个可变长度数据生成第一完整性代码。

3. 发明申请

US20120036286A1 DATA TRANSFER SYSTEM AND DATA TRANSFER METHOD 有权
标题翻译：数据传输系统和数据传输方法
公开(公告)号：US20120036286A1
公开(公告)日：2012-02-09
申请号：US12811500
申请日：2010-06-24
申请人： Osamu Torigoe , Tetsuya Kojima
发明人： Osamu Torigoe , Tetsuya Kojima
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/38
摘要： An efficient transfer of data including a plurality of data sections is achieved. In a data transfer system including a first DMA 1142 of a channel control unit 11 and an MP 122 of a processor unit 12 that sets a transfer parameter in the first DMA 1142, while CKD format data 1400 is transferred from a cache memory 14 to a memory 113 of the channel control unit 11, the MP 122 acquires a C field 1411 from the cache memory 14 and sets a transfer parameter in the first DMA 1142 on the basis of the acquired C field 1411, the transfer parameter having attached thereto the C field 1411 and being used for transferring a K field 1412 from the cache memory 14 to the memory 113. The first DMA 1142 retrieves the C field 1411 attached to the transfer parameter, stores the C field 1411 in the memory 113, and transfers the K field from the cache memory 14 to the memory 113 according to the transfer parameter.
摘要翻译：实现了包括多个数据部分的数据的有效传送。在包括信道控制单元11的第一DMA 1142和设置第一DMA 1142中的传送参数的处理器单元12的MP 122的数据传输系统中，而CKD格式数据1400从高速缓冲存储器14传送到信道控制单元11的存储器113，MP 122从高速缓存存储器14获取C字段1411，并且基于所获取的C字段1411在第一DMA 1142中设置传送参数，传送参数附加到C 字段1411，用于将K字段1412从高速缓冲存储器14传送到存储器113.第一DMA 1142检索附加到传送参数的C字段1411，将C字段1411存储在存储器113中，并将K 根据传送参数从高速缓冲存储器14到存储器113。

4. 发明授权

US08296478B2 Data transfer system and data transfer method 有权
标题翻译：数据传输系统和数据传输方式
公开(公告)号：US08296478B2
公开(公告)日：2012-10-23
申请号：US12811500
申请日：2010-06-24
申请人： Osamu Torigoe , Tetsuya Kojima
发明人： Osamu Torigoe , Tetsuya Kojima
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/38
摘要： An efficient transfer of data including a plurality of data sections is achieved. In a data transfer system including a first DMA 1142 of a channel control unit 11 and an MP 122 of a processor unit 12 that sets a transfer parameter in the first DMA 1142, while CKD format data 1400 is transferred from a cache memory 14 to a memory 113 of the channel control unit 11, the MP 122 acquires a C field 1411 from the cache memory 14 and sets a transfer parameter in the first DMA 1142 on the basis of the acquired C field 1411, the transfer parameter having attached thereto the C field 1411 and being used for transferring a K field 1412 from the cache memory 14 to the memory 113. The first DMA 1142 retrieves the C field 1411 attached to the transfer parameter, stores the C field 1411 in the memory 113, and transfers the K field from the cache memory 14 to the memory 113 according to the transfer parameter.
摘要翻译：实现了包括多个数据部分的数据的有效传送。在包括信道控制单元11的第一DMA 1142和设置第一DMA 1142中的传送参数的处理器单元12的MP 122的数据传输系统中，而CKD格式数据1400从高速缓冲存储器14传送到信道控制单元11的存储器113，MP 122从高速缓存存储器14获取C字段1411，并且基于所获取的C字段1411在第一DMA 1142中设置传送参数，传送参数附加到C 字段1411，用于将K字段1412从高速缓冲存储器14传送到存储器113.第一DMA 1142检索附加到传送参数的C字段1411，将C字段1411存储在存储器113中，并将K 根据传送参数从高速缓冲存储器14到存储器113。

5. 发明授权

US08495164B2 Data transfer device and data transfer method 有权
标题翻译：数据传输设备和数据传输方式
公开(公告)号：US08495164B2
公开(公告)日：2013-07-23
申请号：US12919176
申请日：2010-06-07
申请人： Osamu Torigoe , Yusuke Yauchi
发明人： Osamu Torigoe , Yusuke Yauchi
IPC分类号： G06F15/167
CPC分类号： G06F13/28
摘要： An object of the present invention is to efficiently perform a data transfer by using a plurality of data transfer devices. A storage apparatus 10 includes: a channel control unit 11 having a first DMA 1142, a second DMA 1112, and a memory 113; a processor unit 12; and a drive control unit 13 that communicates with a storage device 17. When the channel control unit 11 transfers to a host computer 3 data stored in a cache memory 14, the first DMA 1142 receives from a processor unit 12 a setting of a first transfer parameter 151 for the first DMA 1142 containing a second transfer parameter 152 for the second DMA 1112, performs a first data transfer from the cache memory 14 to the memory 113 according to the first transfer parameter 151, and sets the second transfer parameter in the second DMA 1112 thereby to cause the second DMA 1112 to perform a data transfer from the memory 113 to the host computer 3.
摘要翻译：本发明的目的是通过使用多个数据传送装置来有效地执行数据传送。存储装置10包括：具有第一DMA 1142，第二DMA1112和存储器113的信道控制单元11; 处理器单元12; 以及与存储装置17通信的驱动控制单元13.当信道控制单元11向主机计算机3传送存储在高速缓冲存储器14中的数据时，第一DMA 1142从处理器单元12接收第一传送的设置包含第二DMA1112的第二传送参数152的第一DMA 1142的参数151根据第一传送参数151执行从高速缓冲存储器14到存储器113的第一数据传送，并将第二传送参数设置在第二传送参数 DMA 1112，从而使第二DMA1112执行从存储器113到主计算机3的数据传送。

6. 发明申请

US20120185554A1 DATA TRANSFER DEVICE AND DATA TRANSFER METHOD 有权
标题翻译：数据传输设备和数据传输方法
公开(公告)号：US20120185554A1
公开(公告)日：2012-07-19
申请号：US12919176
申请日：2010-06-07
申请人： Osamu Torigoe , Yusuke Yauchi
发明人： Osamu Torigoe , Yusuke Yauchi
IPC分类号： G06F15/167
CPC分类号： G06F13/28
摘要： An object of the present invention is to efficiently perform a data transfer by using a plurality of data transfer devices. A storage apparatus 10 includes: a channel control unit 11 having a first DMA 1142, a second DMA 1112, and a memory 113; a processor unit 12; and a drive control unit 13 that communicates with a storage device 17. When the channel control unit 11 transfers to a host computer 3 data stored in a cache memory 14, the first DMA 1142 receives from a processor unit 12 a setting of a first transfer parameter 151 for the first DMA 1142 containing a second transfer parameter 152 for the second DMA 1112, performs a first data transfer from the cache memory 14 to the memory 113 according to the first transfer parameter 151, and sets the second transfer parameter in the second DMA 1112 thereby to cause the second DMA 1112 to perform a data transfer from the memory 113 to the host computer 3.
摘要翻译：本发明的目的是通过使用多个数据传送装置来有效地执行数据传送。存储装置10包括：具有第一DMA 1142，第二DMA1112和存储器113的信道控制单元11; 处理器单元12; 以及与存储装置17通信的驱动控制单元13.当信道控制单元11向主机计算机3传送存储在高速缓冲存储器14中的数据时，第一DMA 1142从处理器单元12接收第一传送的设置包含第二DMA1112的第二传送参数152的第一DMA 1142的参数151根据第一传送参数151执行从高速缓冲存储器14到存储器113的第一数据传送，并将第二传送参数设置在第二传送参数 DMA 1112，从而使第二DMA1112执行从存储器113到主计算机3的数据传送。

7. 发明授权

US07409486B2 Storage system, and storage control method 失效
标题翻译：存储系统和存储控制方法
公开(公告)号：US07409486B2
公开(公告)日：2008-08-05
申请号：US11389158
申请日：2006-03-27
申请人： Osamu Torigoe , Hideaki Shima , Shouji Katoh
发明人： Osamu Torigoe , Hideaki Shima , Shouji Katoh
IPC分类号： G06F12/00 , G06F13/36 , G06F3/00
CPC分类号： G06F3/0658 , G06F3/0613 , G06F3/0656 , G06F3/0689
摘要： A protocol chip and a bridge are connected to a first bus, while the bridge and a micro processor (MP) are connected to a second bus. The MP generates parameter information and writes it into a local memory (LM), and issues a write command which includes access destination information to this parameter information to a protocol chip. The bridge pre-fetches the parameter information from the LM using the access destination information within the write command which is transferred to the protocol chip via itself, and when receiving a read command from the protocol chip, transmits the parameter information which has been pre-fetched to the protocol chip via the first bus, without passing the read command through to the MP.
摘要翻译：协议芯片和桥连接到第一总线，而桥和微处理器（MP）连接到第二总线。 MP产生参数信息并将其写入本地存储器（LM），并向协议芯片发出包含该参数信息的访问目的地信息的写命令。桥接器使用通过自身传送到协议芯片的写入命令中的访问目的地信息，从LM预取参数信息，并且当从协议芯片接收到读取命令时，发送已经被预处理的参数信息，通过第一个总线提取到协议芯片，而不会将读取命令通过MP。

8. 发明授权

US08103939B2 Storage system and data storage method 失效
标题翻译：存储系统和数据存储方法
公开(公告)号：US08103939B2
公开(公告)日：2012-01-24
申请号：US12155207
申请日：2008-05-30
申请人： Osamu Torigoe , Hideaki Fukuda
发明人： Osamu Torigoe , Hideaki Fukuda
IPC分类号： G06F11/00
CPC分类号： G06F11/108 , G06F2211/1009
摘要： The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device.
摘要翻译：所述存储系统包括被配置为存储从主机系统发送的数据的第一存储器件，被配置为控制来自/到所述第一存储器件的数据的读/写访问的第一存储器件控制器，被配置为计算奇偶校验数据的算术电路单元基于所述数据，被配置为存储所述奇偶校验数据的第二存储器设备，被配置为控制来自/到所述第二存储器设备的奇偶校验数据的读/写访问的第二存储器设备控制器。利用该存储系统，第一存储器件的读取访问速度比第二存储器件的读取速度快。

9. 发明申请

US20090249173A1 Storage system and data storage method 失效
标题翻译：存储系统和数据存储方法
公开(公告)号：US20090249173A1
公开(公告)日：2009-10-01
申请号：US12155207
申请日：2008-05-30
申请人： Osamu Torigoe , Hideaki Fukuda
发明人： Osamu Torigoe , Hideaki Fukuda
IPC分类号： G06F11/07
CPC分类号： G06F11/108 , G06F2211/1009
摘要： The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calculate parity data based on the data, a second memory device configured to store the parity data, a second memory device controller configured to control read/write access of the parity data from/to the second memory device. With this storage system, read access speed of the first memory device is faster than read access speed of the second memory device.
摘要翻译：所述存储系统包括被配置为存储从主机系统发送的数据的第一存储器件，被配置为控制来自/到所述第一存储器件的数据的读/写访问的第一存储器件控制器，被配置为计算奇偶校验数据的算术电路单元基于所述数据，被配置为存储所述奇偶校验数据的第二存储器设备，被配置为控制来自/到所述第二存储器设备的奇偶校验数据的读/写访问的第二存储器设备控制器。利用该存储系统，第一存储器件的读取访问速度比第二存储器件的读取速度快。

10. 发明申请

US20070180180A1 Storage system, and storage control method 失效
标题翻译：存储系统和存储控制方法
公开(公告)号：US20070180180A1
公开(公告)日：2007-08-02
申请号：US11389158
申请日：2006-03-27
申请人： Osamu Torigoe , Hideaki Shima , Shouji Katoh
发明人： Osamu Torigoe , Hideaki Shima , Shouji Katoh
IPC分类号： G06F13/36
CPC分类号： G06F3/0658 , G06F3/0613 , G06F3/0656 , G06F3/0689
摘要： A protocol chip and a bridge are connected to a first bus, while the bridge and a micro processor (MP) are connected to a second bus. The MP generates parameter information and writes it into a local memory (LM), and issues a write command which includes access destination information to this parameter information to a protocol chip. The bridge pre-fetches the parameter information from the LM using the access destination information within the write command which is transferred to the protocol chip via itself, and when receiving a read command from the protocol chip, transmits the parameter information which has been pre-fetched to the protocol chip via the first bus, without passing the read command through to the MP.
摘要翻译：协议芯片和桥连接到第一总线，而桥和微处理器（MP）连接到第二总线。 MP产生参数信息并将其写入本地存储器（LM），并向协议芯片发出包含该参数信息的访问目的地信息的写命令。桥接器使用通过自身传送到协议芯片的写入命令中的访问目的地信息，从LM预取参数信息，并且当从协议芯片接收到读取命令时，发送已经被预处理的参数信息，通过第一个总线提取到协议芯片，而不会将读取命令通过MP。

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