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    • 1. 发明授权
    • Method and apparatus for encoding and decoding an NRZI digital signal
with low DC component and minimum low frequency components
    • 用于对具有低DC分量和最小低频分量的NRZI数字信号进行编码和解码的方法和装置
    • US4626826A
    • 1986-12-02
    • US663148
    • 1984-10-22
    • Shinichi FukudaYuichi Kojima
    • Shinichi FukudaYuichi Kojima
    • H03M7/14G11B20/14G11B20/16H04L25/49H04L3/00
    • G11B20/1426
    • A converted digital signal is provided in an NRZI (non-return to zero, inverted) code with a zero DC component and with a maximum predetermined number of bits between level transitions in the signal. The base digital signal is divided into m-bit base words, each of which is then converted into an n bit converted code word to form a converted digital signal suitable for recording. The n-bit converted code word is selected from a plurality of primary combinations or code words having a DC component substantially equal to zero when NRZI-coded and a plurality of secondary combinations or code words having a DC component with an absolute value of two when NRZI-coded. A variance of the DSV (digital sum variation) of each primary combination when NRZI-coded and a polarity of the DC component of each secondary combination when NRZI-coded are altered in response to the DSV at the exit of the preceding converted digital signal.
    • 经转换的数字信号以零直流分量和信号中电平转换之间的最大预定位数的NRZI(非归零,反相)码提供。 基本数字信号被分成m位基本字,然后将每个基本字转换为n位转换码字,以形成适合于记录的转换数字信号。 从NRZI编码的DC分量基本上等于零的多个主要组合或代码字中选择n比特转换的代码字,以及当具有绝对值为2的DC分量的多个辅助组合或代码字时 NRZI编码。 当NRZI编码的NRZI编码的每个主要组合的DSV(数字和变化)和每个次级组合的DC分量的极性响应于先前转换的数字信号的出口处的DSV而被改变。
    • 2. 发明授权
    • Method and apparatus for converting a digital data
    • 用于转换数字数据的方法和装置
    • US4617552A
    • 1986-10-14
    • US644445
    • 1984-08-27
    • Yuichi KojimaShinichi Fukuda
    • Yuichi KojimaShinichi Fukuda
    • H03M7/14G11B20/14H04L25/49H03M7/00
    • G11B20/1426
    • A method for converting a digital data into an NRZI-coded digital signal is disclosed which is carried out by the steps of first detecting if the value of every even numbered bit of the digital data is digital zero, second detecting if two bits of the detected even numbered bits having digital zero value and a preceding odd numbered bit have a DC component, producing a detecting signal according to the result of the second detecting; and converting the digital data into the NRZI-coded digital signal by using the detecting signal.An apparatus for converting a digital data into an NRZI-coded digital signal is also disclosed which includes a first means for detecting if the value of every even numbered bit of the digital data is digital zero, a second means for detecting if two bits of the detected even numbered bits having digital zero value and a preceding odd numbered bit have a DC component, a means for producing a detecting signal according to the result of the second detecting, and a means for converting the digital data into the NRZI-coded digital signal by using the detecting signal.
    • 公开了一种将数字数据转换为NRZI编码的数字信号的方法,其通过以下步骤来执行:首先检测数字数据的每个偶数位的值是否为数字零,第二检测是否检测到两位 具有数字零值的偶数位和前一奇数位具有DC分量,根据第二检测结果产生检测信号; 并通过使用检测信号将数字数据转换成NRZI编码的数字信号。 还公开了一种用于将数字数据转换成NRZI编码的数字信号的装置,其包括用于检测数字数据的每个偶数位的值是否为数字零的第一装置,用于检测数字数据的两位是否为 检测到的具有数字零值的偶数位和前一奇数位具有DC分量,根据第二检测结果产生检测信号的装置,以及用于将数字数据转换成NRZI编码数字信号的装置 通过使用检测信号。
    • 6. 发明授权
    • Apparatus for decoding BCH code
    • 解除BCH代码的设备
    • US5208815A
    • 1993-05-04
    • US426862
    • 1989-10-26
    • Yuichi Kojima
    • Yuichi Kojima
    • H03M13/00H03M13/15
    • H03M13/15
    • An apparatus for decoding BCH code having first, second and third circuits for generating a syndrome S1, a syndrome S3 and a parity P, respectively from a receiving sequence, a fourth circuit coupled to the first circuit for generating S1.sup.2 from the syndrome S1, a fifth circuit coupled to the first circuit, second circuit and fourth circuit for generating (S1.sup.3 +S3), a Chien search circuit which includes a first generating circuit supplied with the S1 and S1.sub.2 for generating a first stage of error-location polynomial A, where A=S1.alpha..sup.-2n +S1.sup.2 .alpha..sup.-n, and a second generating circuit supplied with the (S1.sup.3 .alpha.+S3) and the A for generating a second stage of error-location polynomial B, wherein B=A+S1.sup.3 +S3, and an error correction and detection logic circuit supplied with the S1, P, (S1.sup.3 +S3), A and B and with a decode selection signal and a BCH code selection signal for generating an error correction or detection signal.