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1. 发明申请

US20060238220A1 Method of using mixed multi-Vt devices in a cell-based design 有权
标题翻译：在基于单元的设计中使用混合多Vt设备的方法
公开(公告)号：US20060238220A1
公开(公告)日：2006-10-26
申请号：US11111281
申请日：2005-04-20
申请人： Shine Chung , Cliff Hou , Mark Chen , Lee-Chung Lu
发明人： Shine Chung , Cliff Hou , Mark Chen , Lee-Chung Lu
IPC分类号： H03K19/0175
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

2. 发明申请

US20070294654A1 METHOD FOR USING MIXED MULTI-VT DEVICES IN A CELL-BASED DESIGN 有权
标题翻译：在基于细胞的设计中使用混合多VT设备的方法
公开(公告)号：US20070294654A1
公开(公告)日：2007-12-20
申请号：US11844698
申请日：2007-08-24
申请人： Shine Chien Chung , Cliff Hou , Mark Chen , Lee-Chung Lu
发明人： Shine Chien Chung , Cliff Hou , Mark Chen , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

3. 发明申请

US20090180237A1 DE-COUPLING CAPACITORS PRODUCED BY UTILIZING DUMMY CONDUCTIVE STRUCTURES INTEGRATED CIRCUITS 有权
标题翻译：通过使用导电结构集成电路生产的脱耦电容器
公开(公告)号：US20090180237A1
公开(公告)日：2009-07-16
申请号：US12410117
申请日：2009-03-24
申请人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
发明人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.
摘要翻译：公开了一种在集成电路中使用虚设导电元件的去耦合电容器模块。解耦模块包括具有一个或多个有源节点的至少一个电路模块和未连接到任何有源节点的至少一个虚拟导电元件，并且通过绝缘区域与高压导体或低压导体分离，以提供去耦合电容。

4. 发明授权

US07262951B2 De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits 有权
标题翻译：通过利用虚拟导电结构集成电路产生的去耦电容器
公开(公告)号：US07262951B2
公开(公告)日：2007-08-28
申请号：US10952259
申请日：2004-09-27
申请人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
发明人： Cliff Hou , Lee-Chung Lu , Chia-Lin Cheng
IPC分类号： H01G4/228
CPC分类号： H01L23/5223 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.
摘要翻译：公开了一种在集成电路中使用虚设导电元件的去耦合电容器模块。解耦模块包括具有一个或多个有源节点的至少一个电路模块和未连接到任何有源节点的至少一个虚拟导电元件，并且通过绝缘区域与高电压导体或低压导体分离，以提供去耦合电容。

5. 发明授权

US06789248B1 Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization 有权
标题翻译：执行电阻和电容（RC）参数定制以更好的时序闭合的方法和装置导致物理合成和优化
公开(公告)号：US06789248B1
公开(公告)日：2004-09-07
申请号：US10178401
申请日：2002-06-24
申请人： Lee-Chung Lu , Cliff Hou , Chia-Lin Cheng , Chung-Hsing Wang , Hsing-Chien Huang , Yee-Wen Chen , Tsui-Ping Wang
发明人： Lee-Chung Lu , Cliff Hou , Chia-Lin Cheng , Chung-Hsing Wang , Hsing-Chien Huang , Yee-Wen Chen , Tsui-Ping Wang
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments. The time delay resulting from the physical interconnects is extracted from the timing analysis of the electronic device and from the timing estimate performed during the physical synthesis. The time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis is then compared. The resistance and capacitance unit values used during the timing synthesis are then adjusted. The calibration is repeatedly executed until time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis are correlated.
摘要翻译：用于设计电子设备的方法和系统调节在电子设备的物理合成期间的初步时序分析中使用的电阻和电容值。物理合成使用电阻和电容单位值来确定元件电路的列表。电阻和电容单位值通过预先放置最初合成的组件电路来校准，以创建描述电子设备内的组件电路的物理位置的列表。执行互连的初步路由以创建描述形成组件电路的每个互连的物理线段的网络的列表。电子设备的定时分析确定由组件电路和物理线段网络产生的延迟。从物理互连产生的时间延迟从电子设备的定时分析以及在物理合成期间执行的定时估计提取。然后对来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计进行比较。然后调整在定时合成期间使用的电阻和电容单位值。重复执行校准，直到来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计相关。

6. 发明授权

US07640520B2 Design flow for shrinking circuits having non-shrinkable IP layout 有权
标题翻译：具有不可收缩IP布局的收缩电路的设计流程
公开(公告)号：US07640520B2
公开(公告)日：2009-12-29
申请号：US11807640
申请日：2007-05-30
申请人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.
摘要翻译：提供了一种用于处理集成电路的方法。该方法包括提供具有第一标度的第一集成电路，其中第一集成电路包括包含第一知识产权（IP）布局的可收缩电路和包括第二IP布局的不可收缩电路; 以及生成具有小于所述第一刻度的第二刻度的第二集成电路。产生第二集成电路的步骤包括将可收缩集成电路收缩到第二刻度。该方法还包括将第二IP布局与不可收缩电路合并以产生最终集成电路。

7. 发明申请

US20080270813A1 Mother/daughter switch design with self power-up control 有权
标题翻译：母/子开关设计具有自上电控制功能
公开(公告)号：US20080270813A1
公开(公告)日：2008-10-30
申请号：US11789721
申请日：2007-04-24
申请人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
发明人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
摘要翻译：为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路以及耦合到电路块和第二控制电路的母电路。在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。此外，可以使用旁路电路来减少泄漏电流。

8. 发明授权

US07281230B2 Method of using mixed multi-Vt devices in a cell-based design 有权
标题翻译：在基于单元的设计中使用混合多Vt设备的方法
公开(公告)号：US07281230B2
公开(公告)日：2007-10-09
申请号：US11111281
申请日：2005-04-20
申请人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
发明人： Shine Chien Chung , Cliff Hou , Kun-Lung Chen , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.
摘要翻译：公开了一种在基于单元的设计中利用混合的低阈值电压（低Vt）和高阈值电压（高Vt）装置的方法，从而可以实现电路速度和功率性能的折衷。使用具有不均匀阈值器件的电池来设计电路，速度或/和功率优化与完全定制的设计相当。

9. 发明授权

US07793130B2 Mother/daughter switch design with self power-up control 有权
标题翻译：母/子开关设计具有自上电控制功能
公开(公告)号：US07793130B2
公开(公告)日：2010-09-07
申请号：US11789721
申请日：2007-04-24
申请人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
发明人： Shih-Hsien Yang , Chung-Hsing Wang , Lee-Chung Lu , Chun-Hui Tai , Cliff Hou
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： System and method for providing power to integrated circuitry with good power-on responsive time and reduced power-on transient glitches. A preferred embodiment comprises a daughter switch coupled to a circuit block, a first control circuit coupled to the daughter circuit, a second control circuit coupled to the first control circuit, and a mother circuit coupled to the circuit block and to the second control circuit. After the daughter switch is turned on by a control signal, the mother switch is not turned on until the daughter switch has discharged (charged) the voltage potential across power rails of the mother circuit to a point where glitches are minimized. The second control circuit turns on the mother circuit when the reduced voltage potential is reached, with a signal produced by the first control circuit reflects the voltage potential. Furthermore, a bypass circuit can be used to reduce leakage current.
摘要翻译：为集成电路提供电源的系统和方法具有良好的上电响应时间和减少的上电瞬态毛刺。优选实施例包括耦合到电路块的子开关，耦合到子电路的第一控制电路，耦合到第一控制电路的第二控制电路和耦合到电路块和第二控制电路的母电路。在通过控制信号接通子开关之后，母开关直到子开关已经将母电路的电源轨上的电压放电（充电）到毛刺最小化的位置为止。当达到降低的电压电位时，第二控制电路接通母电路，由第一控制电路产生的信号反映电压电位。此外，可以使用旁路电路来减少泄漏电流。

10. 发明申请

US20080229259A1 Design flow for shrinking circuits having non-shrinkable IP layout 有权
标题翻译：具有不可收缩IP布局的收缩电路的设计流程
公开(公告)号：US20080229259A1
公开(公告)日：2008-09-18
申请号：US11807640
申请日：2007-05-30
申请人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
发明人： Chung-Hsing Wang , Lee-Chung Lu , Cliff Hou , Lie-Szu Juang
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5045
摘要： A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.
摘要翻译：提供了一种用于处理集成电路的方法。该方法包括提供具有第一刻度的第一集成电路，其中第一集成电路包括包含第一知识产权（IP）布局的可收缩电路和包括第二IP布局的不可收缩电路; 以及生成具有小于所述第一刻度的第二刻度的第二集成电路。产生第二集成电路的步骤包括将可收缩集成电路收缩到第二刻度。该方法还包括将第二IP布局与不可收缩电路合并以产生最终集成电路。

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