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1. 发明授权

US5365090A Hetero bipolar transistor and method of manufacturing the same 失效
标题翻译：异质双极晶体管及其制造方法
公开(公告)号：US5365090A
公开(公告)日：1994-11-15
申请号：US45707
申请日：1993-04-14
申请人： Shin-ichi Taka , Kouji Kimura , Hiroshi Naruse , Kuniaki Kumamaru
发明人： Shin-ichi Taka , Kouji Kimura , Hiroshi Naruse , Kuniaki Kumamaru
IPC分类号： H01L29/165 , H01L21/331 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/72
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate, a first silicon layer serving as a collector, a first silicon-germanium layer serving as a base, a second silicon layer serving as a collector, and a second silicon-germanium layer. A side wall of the second silicon-germanium layer is in contact with side walls of the first silicon layer, the first silicon-germanium layer and the second silicon layer. The second silicon-germanium layer is disposed to surround the first silicon layer, the first silicon-germanium layer, and the second silicon layer, and has an energy band gap substantially the same as that of the first silicon-germanium layer.
摘要翻译：该说明书公开了一种异质双极晶体管，其包括半导体衬底，用作集电极的第一硅层，用作基极的第一硅 - 锗层，用作集电极的第二硅层和第二硅 - 锗层。第二硅 - 锗层的侧壁与第一硅层，第一硅 - 锗层和第二硅层的侧壁接触。第二硅锗层被设置为围绕第一硅层，第一硅 - 锗层和第二硅层，并且具有与第一硅 - 锗层基本相同的能带隙。

2. 发明授权

US5399511A Method of manufacturing a hetero bipolar transistor 失效
标题翻译：异质双极晶体管的制造方法
公开(公告)号：US5399511A
公开(公告)日：1995-03-21
申请号：US280199
申请日：1994-07-25
申请人： Shin-ichi Taka , Kouji Kimura , Hiroshi Naruse , Kuniaki Kumamaru
发明人： Shin-ichi Taka , Kouji Kimura , Hiroshi Naruse , Kuniaki Kumamaru
IPC分类号： H01L29/165 , H01L21/331 , H01L29/205 , H01L29/73 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate, a first silicon layer serving as a collector, a first silicon-germanium layer serving as a base, a second silicon layer serving as a collector, and a second silicon-germanium layer. A side wall of the second silicon-germanium layer is in contact with side walls of the first silicon layer, the first silicon-germanium layer and the second silicon layer. The second silicon-germanium layer is disposed to surround the first silicon layer, the first silicon-germanium layer, and the second silicon layer, and has an energy band gap substantially the same as that of the first silicon-germanium layer.
摘要翻译：该说明书公开了一种异质双极晶体管，其包括半导体衬底，用作集电极的第一硅层，用作基极的第一硅 - 锗层，用作集电极的第二硅层和第二硅 - 锗层。第二硅 - 锗层的侧壁与第一硅层，第一硅 - 锗层和第二硅层的侧壁接触。第二硅锗层被设置为围绕第一硅层，第一硅 - 锗层和第二硅层，并且具有与第一硅 - 锗层基本相同的能带隙。

3. 发明授权

US5356821A Method for manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5356821A
公开(公告)日：1994-10-18
申请号：US104907
申请日：1993-08-12
申请人： Hiroshi Naruse , Shin-ichi Taka
发明人： Hiroshi Naruse , Shin-ichi Taka
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L29/49 , H01L29/737 , H01L21/265
CPC分类号： H01L29/7378 , H01L21/8248 , H01L21/8249 , H01L29/4966 , Y10S148/009
摘要： A semiconductor integrated circuit according to the present invention comprises a semiconductor substrate, a plurality of MOS field effect transistors each formed on a surface region of the semiconductor substrate and having source and drain regions, a gate insulating film formed on a region between the source and drain regions, and a gate electrode formed on the gate insulating film. The gate electrode includes a polycrystalline SiGe-mixed crystal which is expressed by Si.sub.1-x Ge.sub.x (1>x>0).
摘要翻译：根据本发明的半导体集成电路包括半导体衬底，多个MOS场效应晶体管，其各自形成在半导体衬底的表面区域上并具有源极和漏极区，栅极绝缘膜形成在源极和源极之间的区域上漏极区域和形成在栅极绝缘膜上的栅电极。栅电极包括由Si1-xGex（1> x> 0）表示的多晶SiGe混合晶体。

4. 发明授权

US5102826A Method of manufacturing a semiconductor device having a silicide layer 失效
标题翻译：制造具有硅化物层的半导体器件的方法
公开(公告)号：US5102826A
公开(公告)日：1992-04-07
申请号：US610216
申请日：1990-11-09
申请人： Jiro Ohshima , Shin-ichi Taka , Toshiyo Motozima , Hiroshi Naruse
发明人： Jiro Ohshima , Shin-ichi Taka , Toshiyo Motozima , Hiroshi Naruse
IPC分类号： H01L21/265 , H01L21/28 , H01L21/285
CPC分类号： H01L21/26506 , H01L21/28518 , Y10S148/106
摘要： According to the method of manufacturing a semiconductor device of the present invention, an insulation film is formed on a silicon substrate, and a resist film having a predetermined pattern is formed on the insulation film, followed by forming an opening on the insulation film with the resist film performing as a mask. Then, an impurity having conductivity are implanted into said silicon substrate with the resist film performing as a mask and silicon ions are implanted into the silicon substrate with the resist film performing as a mask. After that, the resist film is removed. Further, a refractory metal film which covers at least the opening is formed. Moveover, a diffusion layer which causes electrical activation of the impurity having conductivity is formed by annealing, followed by formation a silicide layer at where the surfaces of the silicon substrate and the metal film meet.
摘要翻译：根据本发明的半导体器件的制造方法，在硅衬底上形成绝缘膜，在绝缘膜上形成具有预定图案的抗蚀剂膜，然后在绝缘膜上形成开口作为掩模的抗蚀膜。然后，将具有导电性的杂质注入到所述硅衬底中，并以抗蚀剂膜作为掩模将硅离子注入到硅衬底中，并将硅离子注入到硅衬底中。之后，除去抗蚀剂膜。此外，形成至少覆盖开口的难熔金属膜。通过退火形成引起具有导电性的杂质的电活化的扩散层，随后在硅衬底和金属膜的表面相遇处形成硅化物层。

5. 发明授权

US5488002A Method for manufacturing self-aligned bipolar transistors using double diffusion 失效
标题翻译：使用双扩散制造自对准双极晶体管的方法
公开(公告)号：US5488002A
公开(公告)日：1996-01-30
申请号：US302199
申请日：1994-09-08
申请人： Koji Kimura , Shin-ichi Taka
发明人： Koji Kimura , Shin-ichi Taka
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732 , H01L21/265
CPC分类号： H01L29/66272 , Y10S148/01 , Y10S148/011 , Y10S148/035
摘要： Manufacturing a double polysilicon layer self-aligned type bipolar transistor. A polysilicon layer for emitter impurity diffusion is formed prior to the formation of a polysilicon layer for leading out a base. A first polysilicon layer containing impurities for base impurity diffusion is deposited over the entire surface of a semiconductor structure. After the first polysilicon layer is patterned into a predetermined shape, an intrinsic base layer is formed by thermally diffusing impurities from a base impurity diffusion source. Subsequently, a second polysilicon layer containing emitter impurities is formed over the base impurity diffusion source, and then patterning is performed such that the first and second polysilicon layers remain in a region narrower than the base impurity diffusion source. Thereafter, an emitter layer is formed by thermal diffusion.
摘要翻译：制造双晶硅层自对准型双极晶体管。在形成用于引出基底的多晶硅层之前，形成用于发射体杂质扩散的多晶硅层。含有用于基底杂质扩散的杂质的第一多晶硅层沉积在半导体结构的整个表面上。在将第一多晶硅层图案化成预定形状之后，通过从杂质扩散源热扩散杂质形成本征基极层。随后，在基极杂质扩散源上形成含有发射极杂质的第二多晶硅层，然后进行图案化，使得第一和第二多晶硅层保持在比基极杂质扩散源窄的区域。此后，通过热扩散形成发射极层。

6. 发明授权

US4975381A Method of manufacturing super self-alignment technology bipolar transistor 失效
标题翻译：制造超自对准技术双极晶体管的方法
公开(公告)号：US4975381A
公开(公告)日：1990-12-04
申请号：US492488
申请日：1990-03-12
申请人： Shin-ichi Taka , Jiro Ohshima
发明人： Shin-ichi Taka , Jiro Ohshima
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L21/60 , H01L29/732
CPC分类号： H01L21/76897 , H01L21/28525 , H01L29/66272 , Y10S148/011 , Y10S148/124
摘要： This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched. The size of the base region on the major surface of the semiconductor substrate is defined by the size of the second opening.
摘要翻译：本发明公开了一种制造SST双极型晶体管的方法，该制造方法能够限定SST双极型晶体管的基极区域的尺寸。在半导体基板的主表面上的双极晶体管形成区域中依次形成用作间隔物的绝缘膜和间隔膜。此后，间隔膜被图案化成用于限定基部区域的尺寸的间隔膜图案。在间隔膜图案上依次形成第二绝缘膜，基极图案和第三绝缘膜。形成通过第二绝缘膜到达间隔膜图案的第一开口，基极图案和第三绝缘膜。从第一开口蚀刻间隔膜图案以形成直径大于第一开口直径的第二开口。在第二开口中暴露的绝缘膜被蚀刻。半导体基板的主表面上的基极区域的尺寸由第二开口的尺寸限定。

7. 发明授权

US4717682A Method of manufacturing a semiconductor device with conductive trench sidewalls 失效
标题翻译：制造具有导电沟槽侧壁的半导体器件的方法
公开(公告)号：US4717682A
公开(公告)日：1988-01-05
申请号：US830928
申请日：1986-02-19
申请人： Shin-ichi Taka , Jiro Ohshima , Masahiro Abe , Masaharu Aoyama
发明人： Shin-ichi Taka , Jiro Ohshima , Masahiro Abe , Masaharu Aoyama
IPC分类号： H01L21/76 , H01L21/265 , H01L21/302 , H01L21/3065 , H01L21/74 , H01L21/283
CPC分类号： H01L21/743
摘要： A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底的主表面上依次形成掩埋区域和外延层，沿着延伸到掩埋区域的环形沟槽形成导电层，用环形沟槽填充绝缘材料，并在由所述掩埋区域围绕的所述外延层中形成功能元件，并在所述环形沟槽内形成所述绝缘材料。在该方法中，沿着环形沟槽形成导电层的步骤是通过形成延伸穿过所述掩埋区域的环形沟槽以及仅在所述环形沟槽的侧壁表面上沉积导电层的步骤来执行的。

8. 发明授权

US5244533A Method of manufacturing bipolar transistor operated at high speed 失效
标题翻译：制造高速运行的双极晶体管的方法
公开(公告)号：US5244533A
公开(公告)日：1993-09-14
申请号：US815786
申请日：1992-01-02
申请人： Koji Kimura , Shin-ichi Taka
发明人： Koji Kimura , Shin-ichi Taka
IPC分类号： H01L21/331 , H01L29/10
CPC分类号： H01L29/66272 , H01L29/1004 , Y10S148/01 , Y10S148/124
摘要： According to this invention, in a method of manufacturing a bipolar transistor, a first oxide film, a nitride film, a first polysilicon film containing boron, and a second oxide film are formed on a substrate. A first opening is formed in the second oxide film and the first polysilicon film. The nitride film and the first oxide film are etched in and near the first opening to form overhung portions between the substrate and the first semiconductor film around the first opening. A second polysilicon film for burying the overhung portions is formed on the entire surface of the resultant structure. Thereafter, boron in the second polysilicon film is thermally diffused in the substrate to form an external base region and a link region. The second polysilicon film is etched to leave the second polysilicon film at only the overhung portions. After an internal base region formed in the substrate. Thereafter, an emitter region formed in the internal base region.
摘要翻译：根据本发明，在制造双极晶体管的方法中，在基板上形成第一氧化膜，氮化物膜，含有硼的第一多晶硅膜和第二氧化物膜。在第二氧化物膜和第一多晶硅膜中形成第一开口。在第一开口内和附近蚀刻氮化物膜和第一氧化物膜，以在第一开口周围的基板和第一半导体膜之间形成悬垂部分。用于掩埋悬臂部分的第二多晶硅膜形成在所得结构的整个表面上。此后，第二多晶硅膜中的硼在衬底中热扩散以形成外部基极区域和连接区域。蚀刻第二多晶硅膜以仅在悬垂部分离开第二多晶硅膜。在形成在衬底中的内部基极区域之后。此后，形成在内部基极区域中的发射极区域。

9. 发明授权

US5148252A Bipolar transistor 失效
标题翻译：双极晶体管
公开(公告)号：US5148252A
公开(公告)日：1992-09-15
申请号：US837099
申请日：1992-02-18
申请人： Shin-ichi Taka
发明人： Shin-ichi Taka
IPC分类号： H01L21/331 , H01L21/60 , H01L29/417 , H01L29/423 , H01L29/732 , H01L29/737
CPC分类号： H01L21/76897 , H01L29/41708 , H01L29/42304 , H01L29/66242 , H01L29/66303 , H01L29/7322 , H01L29/7375
摘要： A bipolar transistor includes a p-type external base region formed on the major surface of an n-type semiconductor substrate, a plurality of p-type internal base regions formed to be surrounded by the external base region, and emitter regions of a first conductivity type respectively formed in the internal base regions. An oxide film and a nitride film, stacked on each other, extend outward from an outer peripheral portion of the external base region on the major surface of the semiconductor substrate, and define openings therein. A p-type semiconductor film is formed on the external base region in the openings. A first conductive layer having a p-type semiconductor is formed on the nitride film and the semiconductor film. Side-wall-like oxide films are formed on side wall portions, of the semiconductor film and the first conductive layer, opposite to the emitter regions. A second conductive layer having an n-type semiconductor and serving as an emitter electrode extraction portion is formed on the side-wall-like oxide films to be in contact with the emitter regions.
摘要翻译：双极晶体管包括形成在n型半导体衬底的主表面上的p型外部基极区域，形成为被外部基极区域包围的多个p型内部基极区域和第一导电性的发射极区域分别形成在内部基极区域中。层叠的氧化物膜和氮化物膜从半导体衬底的主表面上的外部基极区域的外周部向外侧延伸，并且在其中限定开口。 p型半导体膜形成在开口中的外部基极区域上。在氮化物膜和半导体膜上形成具有p型半导体的第一导电层。在与发射极区域相对的半导体膜和第一导电层的侧壁部分上形成有侧壁状氧化物膜。在侧壁状氧化物膜上形成具有n型半导体并用作发射极电极提取部分的第二导电层与发射极区域接触。

10. 发明授权

US5204276A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5204276A
公开(公告)日：1993-04-20
申请号：US645313
申请日：1991-01-24
申请人： Hiroomi Nakajima , Nobuyuki Itoh , Hiroyuki Nihira , Eiryo Tsukioka , Kenji Hirakawa , Shin-ichi Taka , Hideki Takada , Yasuhiro Katsumata , Toshio Yamaguchi
发明人： Hiroomi Nakajima , Nobuyuki Itoh , Hiroyuki Nihira , Eiryo Tsukioka , Kenji Hirakawa , Shin-ichi Taka , Hideki Takada , Yasuhiro Katsumata , Toshio Yamaguchi
IPC分类号： H01L21/033 , H01L21/225 , H01L21/285 , H01L21/331
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/2257 , H01L21/28525 , Y10S148/009 , Y10S148/124
摘要： In the method of manufacturing a semiconductor device, a buffer oxide film, an oxidation-resistant film and a first poly-Si film containing a p-type impurity are successively formed to form a laminate structure on the n-type collector region, followed by forming a protective oxide film by CVD. Then, an opening portion reaching the oxidation-resistant film is formed, followed by forming a second protective insulation film to cover the surface of the first poly-Si film exposed at the side wall of the opening portion. The oxidation-resistant film is excessively etched using the protective insulation films as an etching mask so as to expose the buffer oxide film and to form a bore below the first poly-Si film. The exposed buffer oxide film is removed, followed by filling the bore with a second poly-Si film. Then, a heat treatment is performed under an oxidative atmosphere to form a thermal oxide film covering the surface of the second poly-Si film. At the same time, the p-type impurity contained in the first poly-Si film is diffused through the second poly-Si film into the collector region to form a p-type outer base region. Further, a p-type inner base region, n-type emitter region and an emitter electrode are formed.
摘要翻译：在制造半导体器件的方法中，依次形成缓冲氧化膜，耐氧化膜和含有p型杂质的第一多晶硅膜，以在n型集电极区域上形成叠层结构，随后通过CVD形成保护性氧化膜。然后，形成到达抗氧化膜的开口部分，然后形成第二保护绝缘膜以覆盖暴露在开口部分的侧壁处的第一多晶硅膜的表面。使用保护绝缘膜作为蚀刻掩模来过度蚀刻抗氧化膜，以暴露缓冲氧化物膜并在第一多晶硅膜下方形成孔。除去暴露的缓冲氧化物膜，然后用第二多晶硅膜填充孔。然后，在氧化气氛下进行热处理，形成覆盖第二多晶硅膜表面的热氧化膜。同时，包含在第一多晶硅膜中的p型杂质通过第二多晶硅膜扩散到集电区域中，形成p型外基区。此外，形成p型内基区，n型发射极区和发射极。

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