专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5399511A Method of manufacturing a hetero bipolar transistor 失效
标题翻译：异质双极晶体管的制造方法
公开(公告)号：US5399511A
公开(公告)日：1995-03-21
申请号：US280199
申请日：1994-07-25
申请人： Shin-ichi Taka , Kouji Kimura , Hiroshi Naruse , Kuniaki Kumamaru
发明人： Shin-ichi Taka , Kouji Kimura , Hiroshi Naruse , Kuniaki Kumamaru
IPC分类号： H01L29/165 , H01L21/331 , H01L29/205 , H01L29/73 , H01L29/737 , H01L21/265
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate, a first silicon layer serving as a collector, a first silicon-germanium layer serving as a base, a second silicon layer serving as a collector, and a second silicon-germanium layer. A side wall of the second silicon-germanium layer is in contact with side walls of the first silicon layer, the first silicon-germanium layer and the second silicon layer. The second silicon-germanium layer is disposed to surround the first silicon layer, the first silicon-germanium layer, and the second silicon layer, and has an energy band gap substantially the same as that of the first silicon-germanium layer.
摘要翻译：该说明书公开了一种异质双极晶体管，其包括半导体衬底，用作集电极的第一硅层，用作基极的第一硅 - 锗层，用作集电极的第二硅层和第二硅 - 锗层。第二硅 - 锗层的侧壁与第一硅层，第一硅 - 锗层和第二硅层的侧壁接触。第二硅锗层被设置为围绕第一硅层，第一硅 - 锗层和第二硅层，并且具有与第一硅 - 锗层基本相同的能带隙。

2. 发明授权

US4485393A Semiconductor device with selective nitride layer over channel stop 失效
标题翻译：具有通道停止的选择性氮化物层的半导体器件
公开(公告)号：US4485393A
公开(公告)日：1984-11-27
申请号：US267420
申请日：1981-05-26
申请人： Kuniaki Kumamaru , Shunichi Hiraki , Toshio Yonezawa
发明人： Kuniaki Kumamaru , Shunichi Hiraki , Toshio Yonezawa
IPC分类号： H01L29/73 , H01L21/31 , H01L21/331 , H01L29/06 , H01L29/34
CPC分类号： H01L29/0638
摘要： A semiconductor device comprises a semiconductor body of one conductivity type, at least one semiconductor region of the opposite conductivity type formed in the semiconductor body and having a surface flush with the surface of the semiconductor body, an insulative or semi-insulative film formed on the semiconductor body or semiconductor region through a passivation layer and having a fixed charge, positive or negative, and an electrode metal layer connected to at least one of the semiconductor body and region and formed locally on the film directly or through a passivation layer. The semiconductor body or region is of N conductivity type when the film has a positive fixed charge and of P conductivity type when the film has a negative fixed charge.
摘要翻译：半导体器件包括一个导电类型的半导体本体，形成在半导体本体中的具有相反导电类型的至少一个半导体区域，并具有与半导体本体的表面齐平的表面，形成在半导体本体的表面上的绝缘或半绝缘膜半导体本体或半导体区域通过钝化层并具有固定电荷，正极或负极以及连接到半导体主体和区域中的至少一个的电极金属层，并且直接或通过钝化层局部形成在膜上。当膜具有负固定电荷时，当膜具有正固定电荷和P导电类型时，半导体本体或区域为N导电类型。

3. 发明授权

US4542400A Semiconductor device with multi-layered structure 失效
标题翻译：具有多层结构的半导体器件
公开(公告)号：US4542400A
公开(公告)日：1985-09-17
申请号：US528473
申请日：1983-09-01
申请人： Shunichi Hiraki , Kuniaki Kumamaru , Yutaka Koshino , Toshio Yonezawa
发明人： Shunichi Hiraki , Kuniaki Kumamaru , Yutaka Koshino , Toshio Yonezawa
IPC分类号： H01L29/73 , H01L21/283 , H01L21/31 , H01L21/314 , H01L21/331 , H01L23/29 , H01L23/58 , H01L29/34 , H01L23/30 , H01L29/40
CPC分类号： H01L23/58 , H01L21/31 , H01L23/291 , H01L2924/0002
摘要： A semiconductor device comprising a substrate means, a semiconductor layer of an N conductivity type formed on the substrate means, a first semiconductor region of a P conductivity type formed in the semiconductor layer and having its exposed major surface, a second semiconductor region of the N conductivity type formed in the first semiconductor region and having its exposed major surface, a first insulation layer means having a positive polarity type of charge and formed on the N semiconductor layer, and a second insulation layer means having a negative polarity type of charge and formed on the P semiconductor region.
摘要翻译：一种半导体器件，包括基板装置，形成在所述基板装置上的N导电类型的半导体层，形成在所述半导体层中并具有其暴露的主表面的P导电类型的第一半导体区域，所述N的第二半导体区域导电类型形成在第一半导体区域中并且具有暴露的主表面，具有正极性类型的电荷并形成在N半导体层上的第一绝缘层装置和形成为负极性类型的电荷的第二绝缘层装置在P半导体区域。

4. 发明授权

US4379726A Method of manufacturing semiconductor device utilizing outdiffusion and epitaxial deposition 失效
标题翻译：利用外扩散和外延沉积制造半导体器件的方法
公开(公告)号：US4379726A
公开(公告)日：1983-04-12
申请号：US147334
申请日：1980-05-06
申请人： Kuniaki Kumamaru , Shunichi Hiraki , Toshio Yonezawa
发明人： Kuniaki Kumamaru , Shunichi Hiraki , Toshio Yonezawa
IPC分类号： H01L21/8222 , H01L21/22 , H01L21/331 , H01L21/74 , H01L21/761 , H01L27/082 , H01L29/73 , H01L21/76
CPC分类号： H01L21/74 , H01L21/2205 , H01L21/761
摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming a first high impurity concentration region of a conductivity type opposite to the conductivity type of a semiconductor substrate in the substrate along the principal surface thereof, depositing a first epitaxial layer of the same conductivity type as the substrate on the entire principal surface thereof, forming a low impurity concentration region of the opposite conductivity type to the substrate in the first epitaxial layer along a surface portion thereof corresponding to the first high impurity concentration region, forming a second high impurity concentration region of the opposite conductivity type to the substrate in the first epitaxial layer along a different surface portion thereof, forming a second epitaxial layer of the opposite conductivity type to the substrate on the first epitaxial layer, thermally treating the resultant intermediate device to cause diffusion of the impurities in the first and second high impurity concentration region into the respective first and second epitaxial layers and also causing diffusion of the impurity in the low impurity concentration region into the entire portion of the first epitaxial layer corresponding to the first high impurity concentration region, and forming an element isolation region of the same conductivity type as the substrate in the second epitaxial layer such that the element isolation region reaches the first epitaxial layer.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：沿着其主表面在衬底中形成与半导体衬底的导电类型相反的导电类型的第一高杂质浓度区域，沉积其第一外延层导电类型作为其整个主表面上的基板，沿着与第一高杂质浓度区域相对应的表面部分，在第一外延层中形成相反导电类型的低杂质浓度区域，形成第二高杂质在与所述第一外延层不同的表面部分与所述第一外延层中的所述衬底相反的导电类型的浓度区域上形成与所述第一外延层上的所述衬底相反的导电类型的第二外延层，热处理所得到的中间器件以引起扩散的杂质在fi 第一和第二高杂质浓度区域进入相应的第一和第二外延层，并且还引起低杂质浓度区域中的杂质扩散到对应于第一高杂质浓度区域的第一外延层的整个部分中，并且形成元素隔离区域与第二外延层中的衬底具有相同的导电类型，使得元件隔离区域到达第一外延层。

5. 发明授权

US5365090A Hetero bipolar transistor and method of manufacturing the same 失效
标题翻译：异质双极晶体管及其制造方法
公开(公告)号：US5365090A
公开(公告)日：1994-11-15
申请号：US45707
申请日：1993-04-14
申请人： Shin-ichi Taka , Kouji Kimura , Hiroshi Naruse , Kuniaki Kumamaru
发明人： Shin-ichi Taka , Kouji Kimura , Hiroshi Naruse , Kuniaki Kumamaru
IPC分类号： H01L29/165 , H01L21/331 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/72
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The specification discloses a hetero bipolar transistor which comprises a semiconductor substrate, a first silicon layer serving as a collector, a first silicon-germanium layer serving as a base, a second silicon layer serving as a collector, and a second silicon-germanium layer. A side wall of the second silicon-germanium layer is in contact with side walls of the first silicon layer, the first silicon-germanium layer and the second silicon layer. The second silicon-germanium layer is disposed to surround the first silicon layer, the first silicon-germanium layer, and the second silicon layer, and has an energy band gap substantially the same as that of the first silicon-germanium layer.
摘要翻译：该说明书公开了一种异质双极晶体管，其包括半导体衬底，用作集电极的第一硅层，用作基极的第一硅 - 锗层，用作集电极的第二硅层和第二硅 - 锗层。第二硅 - 锗层的侧壁与第一硅层，第一硅 - 锗层和第二硅层的侧壁接触。第二硅锗层被设置为围绕第一硅层，第一硅 - 锗层和第二硅层，并且具有与第一硅 - 锗层基本相同的能带隙。

6. 发明授权

US5127989A Method of forming a thin film pattern with a trapezoidal cross section 失效
标题翻译：形成薄膜图案的方法用TRAPEZOIDAL CROSS SECTION
公开(公告)号：US5127989A
公开(公告)日：1992-07-07
申请号：US699327
申请日：1991-05-13
申请人： Hiroshi Haraguchi , Hitoshi Tsuji , Yasuto Otani , Kuniaki Kumamaru
发明人： Hiroshi Haraguchi , Hitoshi Tsuji , Yasuto Otani , Kuniaki Kumamaru
IPC分类号： H01L21/302 , G03F7/20 , G03F7/38 , H01L21/02 , H01L21/027 , H01L21/033 , H01L21/28 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/822 , H01L27/04
CPC分类号： H01L28/20 , G03F7/2022 , G03F7/38 , H01L21/0274 , H01L21/033 , H01L21/28114 , H01L21/31144 , H01L21/32139
摘要： The present invention provides a method of forming a thin film pattern with a trapezoidal cross section. In this method, a resist pattern with an inverted-trapezoidal cross section is formed on a thin film. Using the resist pattern with the inverted-trapezoidal cross section as a mask, the thin film is dry-etched. A resist pattern is left with the resist pattern used as a mask. The resist pattern has a trapezoidal cross section.

7. 发明授权

US4521256A Method of making integrated devices having long and short minority carrier lifetimes 失效
标题翻译：制造具有少量载体寿命长短的集成器件的方法
公开(公告)号：US4521256A
公开(公告)日：1985-06-04
申请号：US531620
申请日：1983-09-13
申请人： Shunichi Hiraki , Hiroshi Kinoshita , Kuniaki Kumamaru , Shigeo Koguchi , Toshio Yonezawa
发明人： Shunichi Hiraki , Hiroshi Kinoshita , Kuniaki Kumamaru , Shigeo Koguchi , Toshio Yonezawa
IPC分类号： H01L21/322 , H01L21/263 , H01L21/265 , H01L21/268 , H01L21/324
CPC分类号： H01L21/324 , H01L21/263 , H01L21/2636 , H01L21/26506 , H01L21/26513 , H01L21/26546 , H01L21/268 , Y10S148/024 , Y10S148/046 , Y10S148/081
摘要： A process for producing a semiconductor device by which the minority carrier lifetime can be selectively changed in a semiconductor device. A radiation beam is irradiated onto the surface of a semiconductor substrate to shorten the minority carrier lifetime. Then ions are selectively implanted into a region in which the minority carrier lifetime is to be recovered. Finally, the resultant structure is annealed.
摘要翻译：一种用于制造半导体器件的方法，其中可以在半导体器件中选择性地改变少数载流子寿命。辐射束照射到半导体衬底的表面上以缩短少数载流子寿命。然后将离子选择性地注入到将要回收少数载流子寿命的区域中。最后，将所得结构退火。

8. 发明授权

US4240096A Fluorine-doped P type silicon 失效
标题翻译：氟掺杂P型硅
公开(公告)号：US4240096A
公开(公告)日：1980-12-16
申请号：US952777
申请日：1978-10-19
申请人： Shunichi Hiraki , Kuniaki Kumamaru , Masaharu Aoyama , Toshio Yonezawa
发明人： Shunichi Hiraki , Kuniaki Kumamaru , Masaharu Aoyama , Toshio Yonezawa
IPC分类号： H01L21/265 , H01L21/761 , H01L29/167 , H01L29/8605
CPC分类号： H01L21/26506 , H01L21/761 , H01L29/167 , H01L29/8605
摘要： A semiconductor device comprising a fluorine ion implantation region which is selectively formed in a semiconductor region and further activated. The fluorine ion implantation region is adapted for use as a high resistance layer or electrical isolation layer.
摘要翻译：一种半导体器件，包括选择性地形成在半导体区域中并进一步活化的氟离子注入区。氟离子注入区适合用作高电阻层或电隔离层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式